EPC2L120N - 5V/3.3V Altera Config Device, 84-Pin PLCC | Intel
MPN: EPC2L120N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.8 | $980.00 |
| 500 | $8.95 | $4,475.00 |
| 1,000 | $7.85 | $7,850.00 |
EPC2L120N Overview
The Configuration Device (config device or EPCS-class successor) is a non-volatile serial memory device used in conjunction with volatile SRAM-based FPGAs to store their configuration bitstream. At power-up the FPGAs' SRAM configuration cells are blank and must be loaded from an external source; the config device provides this non-volatile storage. Within the broader programmable logic ecosystem, the EPC2L120N sits inside the FPGA & CPLD category and the Intel/Altera configuration-device product hierarchy, which historically evolved from the EPC1/EPC1441 to the EPC2 family and was eventually superseded by the EPCS / EPCQ serial flash devices.
Key features include 2.7V to 3.6V operating voltage, in-system programmability through the IEEE Std 1149.1 JTAG interface, daisy-chain support for multi-device configuration, and 8 MHz internal oscillator with programmable clock division. The device supports both FPP (Fast Passive Parallel) at up to 66 MHz data rate and PS (Passive Serial) configuration schemes via Altera's proprietary configuration bus, and includes open-drain CONF_DONE / nSTATUS / nCONFIG pins for handshaking with the target FPGA.
Architecturally, the EPC2L120N integrates a flash memory array, an internal 8 MHz RC oscillator, JTAG TAP controller for ISP, and a configuration controller that arbitrates between JTAG programming and FPGA configuration modes. The flash cell is rated for 100,000 erase/program cycles and supports byte-level page programming with a typical sector-erase time of 2 seconds.
Typical applications include configuring Altera Cyclone II FPGA development boards, APEX 20K / FLEX 10K reference designs, factory-floor control boards, and industrial video / image-processing platforms. Designers select the EPC2L120N when their design targets older Altera SRAM FPGAs and requires multi-voltage (5V tolerant) configuration with high-bit-count storage.
When designing with this part, note that the JTAG pins TMS, TDI, TDO and TCK must be pulled-up to VCCIO through 10 kohm resistors; the nINIT_CONF pin must remain high during normal operation. For new designs targeting Cyclone IV or later, the EPCS / EPCQ serial flash family is recommended over the legacy EPC2 device.
Drop-in alternatives for EPC2L120N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2L120N (same form factor and footprint) β differing in Mounting Type, Operating Temperature, Package, Configuration Interface, Supported FPGA Families.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2L120
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View Datasheet βEPC2C20N
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EPC2C8N
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EPC22LC20
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPC2L120N Maximum Ratings & Electrical Characteristics
| Device Type | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | Intel (formerly Altera) |
| Family | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V |
| 5V Tolerance | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | Up to 66 MHz |
| Configuration Clock (PS) | Up to 33 MHz |
| Internal Oscillator | 8 MHz with programmable divider |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | 100,000 erase/program cycles |
| Package | 84-pin PLCC (J-Lead) |
| Configuration Schemes | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| RoHS Status | unknown |
EPC2L120N Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 2 | DATA0 β Configuration data bit 0 (FPP/PS) |
| Pin 3 | DATA1 β Configuration data bit 1 (FPP/PS) |
| Pin 4 | DATA2 β Configuration data bit 2 (FPP/PS) |
| Pin 5 | DATA3 β Configuration data bit 3 (FPP/PS) |
| Pin 6 | DATA4 β Configuration data bit 4 (FPP/PS) |
| Pin 7 | DATA5 β Configuration data bit 5 (FPP/PS) |
| Pin 8 | DATA6 β Configuration data bit 6 (FPP/PS) |
| Pin 9 | DATA7 β Configuration data bit 7 (FPP/PS) |
| Pin 10 | nCONFIG β Configuration start request from FPGA |
| Pin 11 | nSTATUS β Open-drain status flag to FPGA |
| Pin 12 | CONF_DONE β Open-drain configuration complete flag |
| Pin 13 | DCLK β Configuration clock output to FPGA |
| Pin 14 | TCK β JTAG test clock input |
| Pin 15 | TMS β JTAG test mode select input |
| Pin 16 | TDI β JTAG test data input |
| Pin 17 | TDO β JTAG test data output |
| Pin 18 | VCCIO β I/O supply (3.3V nominal) |
| Pin 19 | VCC β Core supply (5V) |
| Pin 20 | nINIT_CONF β Initialize configuration (active low) |
| Pin 21-83 | I/O / NC β Reserved configuration pins (see datasheet figure 4) |
| Pin 84 | GND β Ground reference |
Typical Applications
EPC2L120N is suitable for 6 applications: Altera Cyclone II FPGA Configuration, APEX 20K / FLEX 10K Reference Designs, Industrial Control Boards, Legacy Test and Measurement Equipment, Video Processing Platforms, Aerospace Avionics (Legacy Programs).
Altera Cyclone II FPGA Configuration
The EPC2L120N stores the configuration bitstream of Altera Cyclone II EP2C5/EP2C8/EP2C20 FPGAs via the Fast Passive Parallel (FPP) interface at up to 66 MHz. Its 165,888-bit flash capacity easily fits Cyclone II bitstreams (typical 1-3 Mbits compressed), while 5V-tolerant I/O permits mixed-voltage boards with 3.3V FPGAs and 5V logic. Designers use this part on Cyclone II development kits and industrial control boards where a parallel configuration bus is preferred over the later EPCS serial flash.
Recommended
APEX 20K / FLEX 10K Reference Designs
Altera APEX 20K and FLEX 10K devices use multi-voltage 5V/3.3V configuration buses where the EPC2L120N's 5V-tolerant I/O shines. Its 165,888-bit storage covers the bitstreams of EPF10K70 / EP20K200, and its JTAG ISP (IEEE 1149.1) allows in-system reprogramming via ByteBlasterMV or USB-Blaster download cables. Reference designs from Altera AN-203 and the APEX 20K development kit use the EPC2L120N as the canonical configuration companion.
Recommended
Industrial Control Boards
Factory automation controllers often retain legacy Altera FPGAs for long lifecycle support (10+ years), where the EPC2L120N's PLCC-84 socketable form factor supports field upgrade and replacement. Its 100,000 program/erase endurance and -40C to +85C operating range suit industrial environments, and the JTAG ISP permits firmware update via boundary-scan without desoldering. Compared to EPCS serial flash, the PLCC socket allows a service technician to swap the config device in seconds.
Recommended
Legacy Test and Measurement Equipment
Logic analyzers, oscilloscopes, and protocol analyzers built on Altera APEX 20K or FLEX 10K platforms use the EPC2L120N to store FPGA firmware because the parallel FPP bus enables fast reconfiguration during self-test routines. The 66 MHz max clock rate is critical for boot-time-sensitive instruments, and the 5V tolerance permits interfacing to older 5V PLDs and analog front ends. The PLCC package also fits the conventional through-hole layouts of 1990s-vintage test equipment.
Recommended
Video Processing Platforms
Broadcast-grade video routers and frame synchronizers built on Altera APEX 20KE FPGAs use the EPC2L120N to store video pipeline firmware. The 165,888-bit capacity fits full bitstreams for EP20K400E and the parallel FPP bus enables rapid reconfig when switching video standards (PAL/NTSC/HD). The 5V-tolerant I/O permits legacy 5V ADC/DAC interfacing alongside 3.3V FPGA banks, simplifying PCB routing on mixed-voltage video boards.
Recommended
Aerospace Avionics (Legacy Programs)
Long-life aerospace programs that locked their FPGA designs on Altera APEX or FLEX 10K devices in the early 2000s continue to source EPC2L120N for sustainment because the FPGAs' pin-compatible configuration interface is unchanged. The device's wide operating voltage range and JTAG ISP support secure in-field reprogramming on the flight line. The PLCC-84 package supports socketed sparing, allowing line-replaceable units to be swapped without board-level rework.
Recommended
Recommended Products Summary
Engineering reference data for EPC2L120N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2L120 | EPC2C20N | EPC2C8N | EPC22LC20 |
|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-Lead) | 100-pin PQFP - different package | 84-pin PLCC - same | 84-pin PLCC - same | 20-pin PLCC - smaller |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Lifecycle Status | Obsolete (as of 2026-09-11) | Obsolete | Obsolete | Obsolete | Obsolete |
| Configuration Schemes | FPP / PS / JTAG / Daisy chain | FPP / PS / JTAG / Daisy chain | FPP / PS / JTAG / Daisy chain | FPP / PS / JTAG / Daisy chain | FPP / PS / JTAG |
| Target FPGA Family | Cyclone II / APEX / FLEX / Mercury / ACEX / Stratix | Cyclone II / APEX / FLEX / Mercury / ACEX / Stratix | Cyclone / APEX / FLEX / ACEX | FLEX / ACEX | FLEX / ACEX / Cyclone |
Key Differentiators
- Largest storage in the EPC2 PLCC family (vs EPC2C20N)
- 5V-tolerant I/O with 3.3V core supply (vs EPCS64)
- 84-pin PLCC socketable form factor (vs EPC2L120 (PQFP-100))
Design Notes
The EPC2L120N requires dual supplies: VCCIO at 2.7V-3.6V for the I/O ring and VCC at 5V (or 3.3V) for the core. Decoupling is critical - place a 0.1uF X7R ceramic cap on each VCC/VCCIO pin with trace length under 2 mm. During JTAG programming, inrush current can spike to 50 mA per I/O bank; ensure bulk decoupling of 10uF tantalum near the device.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 ohm controlled impedance and avoid stubs; pull-ups (10 kohm) on TMS, TDI and TDO to VCCIO are mandatory. The 8-bit DATA bus to the target FPGA should be length-matched within +/-200 mils to preserve setup/hold at 66 MHz FPP. Keep DCLK away from DATA lines to avoid crosstalk; ground guard the bus on both sides.
Common pitfalls with the EPC2L120N include: (1) forgetting the JTAG pull-ups causing ISP failure; (2) using the wrong Quartus programming file (use .pof for EPC2, not .sof); (3) exceeding 5V on JTAG pins when VCCIO is 3.3V (the JTAG pins are 5V-tolerant but the FPGA target may not be); (4) driving CONF_DONE from external source instead of leaving it open-drain; (5) using ByteBlasterMV in PS mode where FPP is required for high-density bitstreams.
Compliance Information
Compliance data not present in verified web sources. EPC2 family pre-dates widespread RoHS reporting; consult Intel product ecology documents for legacy Altera parts.
