EPC2L20 vs EPC2LS20U Comparison
Detailed side-by-side comparison of EPC2L20 by Altera and EPC2LS20U by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2L20 | EPC2LS20U |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.80 | $4.25 |
| Memory Type | Configuration PROM (non-volatile) | β |
| Memory Size | 1.6 Mbit | β |
| Organization | 8-bit byte | β |
| Interface | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) | Altera serial configuration / JTAG |
| Programmability | In-system programmable via JTAG | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (VCCSEL selectable) | β |
| Cascade Support | Yes - multi-device daisy chain | β |
| Boundary Scan | JTAG IEEE 1149.1 BST | β |
| Package | 20-pin PLCC (J-lead) | 20-PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount (PLCC socket compatible) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: Operating Temperature] |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL Level] |
| RoHS Status | RoHS Compliant (per IC Components listing) | β |
| Process Technology | Low-power CMOS | β |
| Target FPGAs | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix | β |
| Product Type | β | In-System Programmable Configuration PROM |
| Memory Density | β | 1.6 Mbit |
| Operating Voltage (VCC) | β | 3.3 V |
| Programming Method | β | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | β | Yes (per "U" suffix) |
| Supported FPGA Families | β | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | β | PS (Passive Serial), AS, FPP |
| JTAG Support | β | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | β | Yes (open-drain programmable polarity) |
| nSTATUS Pin | β | Yes (open-drain error flag) |
| nCONFIG Pin | β | Yes (reset/reconfiguration input) |
| DCLK Output | β | Yes (configuration clock to FPGA) |
| Compliance | β | RoHS (Pb-free per U suffix) |