EPC2L20 - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
MPN: EPC2L20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $41.23 | $41.23 |
| 10 | $38.5 | $385.00 |
| 100 | $33.9 | $3,390.00 |
| 500 | $29.4 | $14,700.00 |
| 1,000 | $25.8 | $25,800.00 |
EPC2L20 Overview
What is a configuration PROM? A configuration PROM is a non-volatile memory device that stores the bitstream for an SRAM-based FPGA. Because SRAM loses its configuration when power is removed, every SRAM-FPGA design requires a boot memory that delivers the bitstream on power-up via a serial or parallel configuration interface. The EPC2L20 belongs to the hierarchy: configuration PROM -> programmable logic support memory -> non-volatile memory -> semiconductor memory IC. Altera's EPC2 family replaced the older EPC1 family with higher density, in-system programmability via IEEE 1532, and lower power consumption.
Key features include 1.6 Mbit of configuration storage organized as 8-bit bytes, in-system programmability through the JTAG (IEEE 1149.1 / IEEE 1532) interface, a cascadable multi-device daisy-chain architecture for higher density systems, and a low-power CMOS process. The device supports both 5.0 V and 3.3 V operation modes selectable via the VCCSEL pin, and integrates JTAG boundary-scan test capability for board-level manufacturability.
The EPC2L20 uses a serial configuration interface that reduces FPGA pin-count overhead, and the cascadable architecture lets multiple EPC2 devices share a single configuration bus on the FPGA, allowing designers to scale up configuration density without changing the FPGA configuration controller. The 3.3 V core with 5 V tolerant I/O simplifies mixed-voltage board designs where older 5 V logic coexists with newer 3.3 V devices.
Typical applications include Altera APEX II and APEX 20K configuration, Stratix and Cyclone FPGA boot memory, multi-FPGA configuration chains for DSP and prototyping boards, and industrial controllers using SRAM-based LUT devices. Engineers select the EPC2L20 when their FPGA configuration bitstream fits within 1.6 Mbit and they require the simplicity of a single-chip configuration solution.
Designers should verify that their compiled FPGA bitstream does not exceed 1.6 Mbit before selecting this device, and ensure that the JTAG chain is correctly terminated for in-system reprogramming. For higher densities, EPC4 or EPC8/EPC16 in the same family provide more storage in larger packages.
This page synthesizes distributor pricing across Nantian, Veswin, Jotrin and FPGAkey alongside pin-to-pin compatible alternatives in the Altera EPC2 family not found in the standalone datasheet.
Drop-in alternatives for EPC2L20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2L20 (same form factor and footprint) — differing in Mounting Type, Package, Memory Type, Operating Temperature, Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LI20
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPC2L20N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.2 / Unit
View Datasheet →EPC1LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EPC2L20 Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (non-volatile) |
| Memory Size | 1.6 Mbit |
| Organization | 8-bit byte |
| Interface | Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) |
| Programmability | In-system programmable via JTAG |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (VCCSEL selectable) |
| Cascade Support | Yes - multi-device daisy chain |
| Boundary Scan | JTAG IEEE 1149.1 BST |
| Package | 20-pin PLCC (J-lead) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| RoHS Status | RoHS Compliant (per IC Components listing) |
| Process Technology | Low-power CMOS |
| Target FPGAs | APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix |
EPC2L20 Pin Configuration
| Pin 1 | nSTATUS — Configuration status (open-drain, pulled low during configuration error) |
| Pin 2 | DATA — Serial configuration data output to FPGA |
| Pin 3 | DCLK — Configuration clock input from FPGA |
| Pin 4 | nCS — Chip select (active low) for cascade mode |
| Pin 5 | nCASC — Cascade output (active low) to next EPC2 device |
| Pin 6 | GND — Ground |
| Pin 7 | TDI — JTAG test data in (IEEE 1149.1) |
| Pin 8 | TMS — JTAG test mode select |
| Pin 9 | TCK — JTAG test clock |
| Pin 10 | nCONFIG — Configuration initiate (input from FPGA) |
| Pin 11 | VCCSEL — I/O voltage select: GND=3.3V I/O, VCC=5.0V I/O |
| Pin 12 | VCC — 3.3 V core supply |
| Pin 13 | OE — Output enable for DATA (active high) |
| Pin 14 | nCE — Chip enable (active low) |
| Pin 15 | GND — Ground |
| Pin 16 | TDO — JTAG test data out |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | GND — Ground |
| Pin 20 | VCC — 3.3 V core supply |
Typical Applications
EPC2L20 is suitable for 6 applications: Altera APEX II FPGA Boot Memory, Stratix FPGA Configuration Storage, Cyclone Series FPGA Configuration, Multi-FPGA Configuration Chains, Industrial Control & Test Equipment, Legacy Avionics & Defense Systems.
Altera APEX II FPGA Boot Memory
The EPC2L20 stores the configuration bitstream for Altera APEX II EP2A15/EP2A25/EP2A40 FPGAs in industrial DSP and telecom line-card designs. With 1.6 Mbit of non-volatile storage the device fits APEX II bitstreams that average 1.0 to 1.4 Mbit after compression, and its serial configuration interface keeps FPGA pin overhead low. The 3.3 V core with 5 V tolerant I/O matches legacy 5 V APEX II boards, while JTAG (IEEE 1532) in-system programming lets field engineers update firmware without removing the PROM.
Recommended
Stratix FPGA Configuration Storage
The EPC2L20 boots early-generation Stratix EP1S10/EP1S20/EP1S25 FPGAs in networking and signal-processing equipment where 1.6 Mbit is sufficient. Designers place the EPC2L20 on the configuration bus and rely on its cascadable architecture if a future Stratix migration needs higher density. The 20-pin PLCC package remains socket-compatible with quick-turn prototyping boards, reducing bring-up time during hardware validation cycles.
Recommended
Cyclone Series FPGA Configuration
The EPC2L20 configures Cyclone EP1C3/EP1C6/EP1C12 devices in cost-sensitive applications such as industrial controllers, video processing and consumer electronics. A 1.6 Mbit PROM comfortably fits compressed Cyclone bitstreams up to EP1C12 density. The PLCC-20 socket footprint is friendly to through-hole rework on legacy boards, and the JTAG interface enables on-board bitstream updates during engineering validation.
Recommended
Multi-FPGA Configuration Chains
Engineers cascade multiple EPC2L20 PROMs on a single configuration bus to support multi-FPGA boards such as DSP prototyping systems and ASIC emulators. The cascadable architecture shares DCLK and DATA across devices, letting the master FPGA sequentially load each PROM. The 1.6 Mbit per device is sufficient for older Stratix and APEX 20K bitstreams, and the JTAG chain can program all cascaded EPC2L20s in one boundary-scan operation.
Recommended
Industrial Control & Test Equipment
The EPC2L20 is widely deployed in industrial controllers, automated test equipment and military/aerospace subsystems that adopted Altera APEX 20K and ACEX 1K families in the early 2000s. Its industrial-grade variants survive harsh factory environments, and the non-volatile boot memory eliminates the need for host microcontrollers to configure the FPGA at power-up. The 20-pin PLCC is socketed for easy field replacement during long-lifecycle maintenance windows.
Recommended
Legacy Avionics & Defense Systems
Defense and avionics programs adopted Altera APEX II and Mercury devices with EPC2L20 configuration memory in the 2000s and continue to maintain these designs today. The PLCC-20 package supports through-hole socketing required by MIL-STD-810 environments, and the in-system programmability simplifies field firmware updates. Sustainment programs use the EPC2L20 alongside industrial-grade FPGAs to extend platform life beyond the original Altera production cycle.
Recommended
Recommended Products Summary
Engineering reference data for EPC2L20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LI20 | EPC2L20N | EPC1LC20 |
|---|---|---|---|---|---|
| Package | PLCC-20 | PLCC-20 (same) | PLCC-20 (same) | PLCC-20 (same) | PLCC-20 (same) |
| Brand | Altera | Altera (same) | Altera (same) | Altera (same) | Altera (same) |
| Memory Size | 1.6 Mbit | 1.6 Mbit (same) | 1.6 Mbit (same) | 1.6 Mbit (same) | ~1 Mbit (older family) |
| Core Voltage | 3.3 V | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) | 5.0 V (EPC1 family) |
| I/O Voltage | 3.3 V or 5.0 V (VCCSEL) | 3.3 V or 5.0 V (same) | 3.3 V or 5.0 V (same) | 3.3 V or 5.0 V (same) | 5.0 V only |
| In-System Programmable | Yes (JTAG IEEE 1532) | Yes (same) | Yes (same) | Yes (same) | No (EPC1 requires external programmer) |
| Temperature Grade | Commercial | Commercial | Industrial (-40C to +85C) | Commercial | Commercial |
Key Differentiators
- Industrial temperature variant available in same footprint (vs EPC2LI20)
- 1.6 Mbit density with in-system programmability (vs EPC1LC20)
- Dual 3.3 V/5.0 V I/O via VCCSEL (vs EPC2TI32)
Design Notes
The EPC2L20 requires a clean 3.3 V core supply (VCCINT) with at least a 0.1 uF decoupling capacitor placed within 5 mm of the VCC pins (pin 12 and pin 20). During configuration, the device can draw transient currents up to 50 mA; bulk decoupling of 10 uF tantalum near the PLCC socket is recommended per Altera's Configuration Handbook. The VCCSEL pin must be tied to either GND (3.3 V I/O) or VCC (5.0 V I/O); leaving it floating risks configuration errors on the DATA output.
Do not exceed 1.6 Mbit when compiling the FPGA bitstream - if the design grows past this density, the EPC2L20 will return a configuration-error pattern on nSTATUS and the FPGA will not enter user mode. For larger designs, cascade a second EPC2 device using the nCASC pin, or migrate to a higher-density EPC4/EPC8 (different package, not drop-in). Always confirm bitstream size in the Altera Quartus fitter report before finalizing the BOM.
Place the EPC2L20 within 50 mm of the FPGA configuration pins to keep the DCLK and DATA traces short and matched. Use a PLCC-20 socket (e.g. AMP 1-822473-1) for field-replaceability and to ease rework on legacy boards. Route the JTAG signals TDI, TMS, TCK and TDO as a daisy chain with 4.7 kohm pull-ups on TMS and TCK; do not share the JTAG chain with other EPC2 devices without proper TAP ordering.
Compliance Information
RoHS compliance confirmed by IC Components listing. Reach, halogen-free and conflict-mineral declarations not present in verified web data; treated as unknown. Not AEC-Q100 qualified - this is a commercial/industrial-grade configuration PROM.
