EPC2L20U vs EPC2L120N Comparison
Detailed side-by-side comparison of EPC2L20U by Altera and EPC2L120N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2L20U | EPC2L120N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.55 | $7.85 |
| Memory Size | 1.6 Mbit | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | β |
| Interface Type | Serial configuration (DCLK/DATA0) | β |
| Programmability | In-system programmable via IEEE 1532 / JTAG | β |
| Supported FPGAs | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K | β |
| Configuration Mode | Single + Cascade (multi-PROM daisy chain) | β |
| Compression Support | Yes (FPGA decompresses bitstream) | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: industrial temp range] |
| Package | 20-PLCC (PLCC-20) | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Socket | β |
| JTAG Support | Yes (IEEE Std 1149.1 boundary scan) | β |
| Pin Count | 20 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Device Type | β | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | β | Intel (formerly Altera) |
| Family | β | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | β | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | β | 2.7 V to 3.6 V |
| 5V Tolerance | β | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | β | Up to 66 MHz |
| Configuration Clock (PS) | β | Up to 33 MHz |
| Internal Oscillator | β | 8 MHz with programmable divider |
| JTAG Interface | β | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | β | 100,000 erase/program cycles |
| Sector Erase Time | β | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | β | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | β | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |