EPC2LC02N vs EPC2L20N Comparison
Detailed side-by-side comparison of EPC2LC02N by Intel and EPC2L20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC02N | EPC2L20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.40 | $17.20 |
| Device Type | Enhanced Configuration Device (Configuration PROM) | β |
| Memory Density | 1.6 Mbit | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | β |
| Interface | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP | β |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| Supported FPGA Families | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Mode | Serial / Parallel / Multi-device daisy-chain | β |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Package | 20-pin PLCC (Plastic Leaded Chip Carrier) | β |
| Package Code | L (PLCC-20, leaded) | β |
| Mounting Type | Surface Mount / Socket | Surface Mount (J-Lead PLCC) |
| JTAG Compliance | IEEE 1149.1 (TAP controller with 4-wire interface) | β |
| DC Input Voltage (absolute max) | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) | β |
| Lead-Free / RoHS | Lead finish version dependent (Pb-free and SnPb variants exist) | β |
| MSL Level | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Programming Cycles | 100 typical (flash endurance, per datasheet) | β |
| Function | β | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Memory Size | β | 1.6 Mbit |
| Programmable Type | β | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | β | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| Package / Case | β | 20-LCC (J-Lead), PLCC-20 |
| Packaging | β | Tube |
| Configuration Interface | β | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | β | Yes (multi-PROM chain via CE control) |
| Programming Method | β | In-system via 4-wire ISP / JTAG-style |
| Pin Count | β | 20 |
| Lead Finish | β | Matte Tin (Pb-free) |
| RoHS Status | β | Compliant |