EPC2LC20 vs EPC1LC20-W Comparison
Detailed side-by-side comparison of EPC2LC20 by Altera and EPC1LC20-W by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC1LC20-W
EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
EPC1LC20-W ObsoleteSpecification Comparison
| Parameter | EPC2LC20 | EPC1LC20-W |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $9.85 |
| Memory Type | Non-volatile configuration PROM | OTP (One-Time Programmable) Configuration PROM |
| Memory Size | 1.6 Mbit | 1 Mbit |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | β |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | β |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | β |
| ISP Voltage Range | 5.0 V or 3.3 V | β |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | β |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | β |
| Package | 20-pin PLCC (J-lead, 9x9 mm) | 20-PLCC J-lead (9x9 mm) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Operating Temperature | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | β |
| RoHS Status | Non-Compliant (original Altera Pb-containing part) | Compliant (Pb-free -W finish) |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | β |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | β |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | β |
| Configuration Clock (DCLK) | β | 8 MHz maximum |
| Supply Voltage | β | 3.3 V and 5.0 V |
| Interface | β | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | β | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | β | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | β | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | β | Yes - stores compressed Altera FPGA bitstreams |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | β | 1 (OTP) |
| Target FPGA Families | β | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |