EPC2LC20NA vs EPC1LI20 Comparison

Detailed side-by-side comparison of EPC2LC20NA by Altera and EPC1LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2LC20NA

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA ⚠ Last Time Buy

Specification Comparison

Parameter EPC2LC20NA EPC1LI20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.50 $8.50
Manufacturer Altera Corporation (Intel Programmable Solutions Group) β€”
Memory Type Configuration PROM (Flash-based, ISP) OTP Configuration PROM (EPROM-based)
Memory Density 1.6 Mbit β€”
Operating Voltage (VCC) 3.3 V β€”
Interface Serial (passive-serial) data output to FPGA β€”
Programmability In-system programmable via IEEE 1532 JTAG β€”
Package 20-pin PLCC (9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
Operating Temperature -40C to +85C (industrial grade) [DATA_NEEDED: operating temperature range]
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury β€”
JTAG Compliance IEEE Std 1149.1 / IEEE 1532 β€”
Configuration Mode Passive Serial (PS) β€”
RoHS Status [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish]
Daisy-Chain Support Yes β€”
Recommended Companion FPGA Altera Cyclone, FLEX 10K, APEX 20K series β€”
Memory Size β€” 1 Mb (1,048,576 bits)
Configuration Interface β€” Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1)
Maximum Configuration Clock β€” 8 MHz
Supply Voltage (VCC) β€” 5.0 V (4.75 V to 5.25 V)
Programming Voltage (VPP) β€” 12.75 V (typical, factory-programmed via JTAG)
Pin Count β€” 20
Cascading Support β€” Yes (nCASC pin for multi-device daisy chain)
Endurance β€” OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase)
JTAG Programming β€” Yes (in-system via IEEE 1149.1)
Compatible FPGA Families β€” FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury
MSL Level β€” 1 (per Partstack datasheet record)

Datasheets & Resources

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