EPC2LC20NA vs EPC2LC20V Comparison

Detailed side-by-side comparison of EPC2LC20NA by Altera and EPC2LC20V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2LC20NA

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA ⚠ Last Time Buy

Specification Comparison

Parameter EPC2LC20NA EPC2LC20V
Brand Altera Intel
Category Memory ICs FPGA & CPLD
Lifecycle Status Last_time_buy Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $5.50 $9.95
Manufacturer Altera Corporation (Intel Programmable Solutions Group) β€”
Memory Type Configuration PROM (Flash-based, ISP) β€”
Memory Density 1.6 Mbit β€”
Operating Voltage (VCC) 3.3 V 3.0 V to 3.6 V (3.3 V typ.)
Interface Serial (passive-serial) data output to FPGA β€”
Programmability In-system programmable via IEEE 1532 JTAG β€”
Package 20-pin PLCC (9x9 mm) PLCC-20 (JEDEC MO-047)
Mounting Type Surface Mount (PLCC socket compatible) β€”
Operating Temperature -40C to +85C (industrial grade) -40C to +85C (industrial)
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury β€”
JTAG Compliance IEEE Std 1149.1 / IEEE 1532 β€”
Configuration Mode Passive Serial (PS) β€”
RoHS Status [DATA_NEEDED: rohs status] β€”
Daisy-Chain Support Yes β€”
Recommended Companion FPGA Altera Cyclone, FLEX 10K, APEX 20K series β€”
Product Type β€” Flash Configuration Device (FPGA configuration PROM)
Memory Size β€” 1.6 Mb (1,678,336 bits)
Configuration Interface β€” Serial (Passive Serial) or 8-bit parallel
Maximum Configuration Clock β€” 10 MHz
Program/Erase Cycles β€” 100,000 cycles minimum
Data Retention β€” 20 years minimum
JTAG Support β€” IEEE 1149.1 Boundary Scan, in-system programmable
Storage Temperature β€” -65C to +150C
Lead-Free / RoHS β€” Lead-free (V suffix), RoHS compliant
Compatible FPGAs β€” Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000
On-chip Oscillator β€” Yes (generates DCLK)
Configuration Time (typical) β€” Depends on FPGA bitstream length and clock mode
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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