EPC2LC20V - Altera 1.6Mb Flash Config Device, PLCC-20 | Intel
MPN: EPC2LC20V ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EPC2LC20V Overview
A Configuration Device is a non-volatile memory that stores the FPGA's configuration bitstream and serially or byte-parallel delivers it to the FPGA's DATA, DCLK, and nCONFIG pins at power-up. In the broader taxonomy, an FPGA configuration PROM sits below non-volatile memory > Flash memory > PROM > configuration memory within the semiconductor hierarchy. It bridges the volatile SRAM-LUT architecture (which loses configuration when power is removed) with a permanent, field-updatable boot source - eliminating the need for external boot PROMs from third-party vendors and enabling remote firmware revision via JTAG.
Key features include 1.6 Mb of usable configuration storage (more than 4x the original EPC1), a flexible serial or 8-bit parallel configuration interface, an on-chip oscillator to generate DCLK, JTAG boundary-scan support (IEEE 1149.1), and in-system programmability through JTAG without external programmer hardware. The PLCC-20 footprint provides rugged mechanical compliance for industrial through-hole and socketed assemblies, and the device is compatible with the older EPC1 / EPC1064 / EPC1441 pinouts on a 1:1 basis within the same package family.
Typical applications include standalone boot of Altera Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, ACEX 1K, APEX 20K, APEX II, and older FLEX 10K / FLEX 8000 devices in industrial controllers, telecommunications line cards, test & measurement chassis, and military/aerospace FPGA systems. Because the EPC2 supports both serial and 8-bit byte-wide configuration, a single PROM can serve either low-pin-count or high-throughput FPGA boot scenarios.
When designing with this device, verify that the FPGA's configuration mode (AS, PS, or JTAG-only) matches the EPC2's supported modes, since the EPC2 is intended for PS (Passive Serial) and JTAG programming - it does not support Altera Active Serial (AS) mode, which uses serial Flash such as EPCS / EPCQ devices. Add a 0.1 uF decoupling capacitor near the VCC pin and ensure nINIT_CONF and nSTATUS are correctly tied to the FPGA's nCONFIG / nSTATUS pins.
This page synthesizes distributor pricing, drop-in compatible configuration-memory alternatives, JTAG programming notes, and PLCC-20 package cross-references not found in the original Altera datasheet - giving a single source for engineers re-spinning legacy Altera FPGA designs.
Drop-in alternatives for EPC2LC20V — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20V (same form factor and footprint) — differing in Memory Type, Package, Configuration Interface, Supported FPGA Families, Memory Size.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20NA
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5.5 / Unit
View Datasheet →EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20N
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPC1441LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
Contact for price
View Datasheet →EPC2LC20V Maximum Ratings & Electrical Characteristics
| Product Type | Flash Configuration Device (FPGA configuration PROM) |
| Memory Size | 1.6 Mb (1,678,336 bits) |
| Configuration Interface | Serial (Passive Serial) or 8-bit parallel |
| Maximum Configuration Clock | 10 MHz |
| Operating Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typ.) |
| Program/Erase Cycles | 100,000 cycles minimum |
| Data Retention | 20 years minimum |
| JTAG Support | IEEE 1149.1 Boundary Scan, in-system programmable |
| Package | PLCC-20 (JEDEC MO-047) |
| Operating Temperature | -40C to +85C (industrial) |
| Storage Temperature | -65C to +150C |
| Lead-Free / RoHS | Lead-free (V suffix), RoHS compliant |
| Compatible FPGAs | Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000 |
| On-chip Oscillator | Yes (generates DCLK) |
| Configuration Time (typical) | Depends on FPGA bitstream length and clock mode |
EPC2LC20V Pin Configuration
| Pin 1 | DATA[0] — Serial configuration data output (bit 0 of byte-wide mode) |
| Pin 2 | DATA[1] — Configuration data output bit 1 (byte-wide mode) |
| Pin 3 | DATA[2] — Configuration data output bit 2 (byte-wide mode) |
| Pin 4 | nCS — Chip select (active low) for byte-wide mode |
| Pin 5 | nSTATUS — Open-drain status flag to FPGA nSTATUS |
| Pin 6 | OE — Output enable (active low) for serial data |
| Pin 7 | nCONFIG — Configuration initiate / reset from FPGA |
| Pin 8 | DCLK — Configuration clock to FPGA (generated internally by EPC2) |
| Pin 9 | VCC — +3.3 V power supply |
| Pin 10 | GND — Ground |
| Pin 11 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 12 | TMS — JTAG Test Mode Select |
| Pin 13 | TCK — JTAG Test Clock |
| Pin 14 | TDO — JTAG Test Data Out |
| Pin 15 | nINIT_CONF — Initiate configuration (active low) to FPGA nCONFIG |
| Pin 16 | nCE — Chip enable cascade (active low) for multi-PROM daisy-chain |
| Pin 17 | DATA[3] — Configuration data output bit 3 (byte-wide mode) |
| Pin 18 | DATA[4] — Configuration data output bit 4 (byte-wide mode) |
| Pin 19 | DATA[5] — Configuration data output bit 5 (byte-wide mode) |
| Pin 20 | DATA[6]/DATA[7] — Configuration data output bits 6 and 7 (byte-wide mode, shared pin) |
Typical Applications
EPC2LC20V is suitable for 6 applications: Cyclone FPGA Boot PROM, Stratix Telecom Line Card, APEX 20K Industrial Controller, Test & Measurement Chassis, Military / Aerospace FPGA System, FPGA Development Board Boot Loader.
Cyclone FPGA Boot PROM
The EPC2LC20V's 1.6 Mb of Flash storage comfortably covers the configuration bitstream of Altera Cyclone, Cyclone II, and Cyclone III devices in Passive Serial mode. With 10 MHz DCLK the EPC2 generates the entire bitstream in under 200 ms for a typical Cyclone II EP2C35 design. The PLCC-20 socketed package allows field replacement without desoldering, and JTAG in-system programming lets a technician rewrite the bitstream at any point in the product lifecycle - ideal for industrial controller firmware revisions.
Recommended
Stratix Telecom Line Card
Altera Stratix and Stratix II FPGAs in telecom line cards require reliable non-volatile boot storage that survives 20+ years in service. The EPC2LC20V delivers exactly that: 1.6 Mb Flash with 20-year data retention, industrial -40C to +85C operation, and JTAG in-system programming per IEEE 1149.1 so firmware updates can be pushed to deployed line cards remotely. The 8-bit parallel configuration mode available on EPC2 cuts Stratix boot time roughly 8x versus serial boot, helping meet fast-restart requirements after power cycling.
Recommended
APEX 20K Industrial Controller
Legacy Altera APEX 20K and APEX II designs in long-life industrial controllers still rely on EPC1/EPC2 family PROMs for boot. The EPC2LC20V offers 4x the storage of the original EPC1LC20 (1.6 Mb vs 0.4 Mb), enabling APEX 20K200 / APEX 20K400 bitstreams without squeezing. The PLCC-20 footprint is pin-compatible with EPC1 sockets, simplifying inventory and replacement in legacy systems. 100,000 program/erase cycles support frequent firmware revision during the controller's 15-20 year service life.
Recommended
Test & Measurement Chassis
Modular T&M chassis typically use multiple Altera FPGAs - one per measurement slot - each requiring its own configuration PROM. The EPC2LC20V in PLCC-20 provides the rugged mechanical form factor needed for socketed field service, and the JTAG chain lets the chassis controller reconfigure all FPGAs simultaneously. With 1.6 Mb Flash per device, a single EPC2LC20V covers the bitstream of mid-complexity Altera ACEX 1K, FLEX 10K, or smaller Cyclone II devices commonly used in instrument digitizer and signal-conditioning cards.
Recommended
Military / Aerospace FPGA System
Ruggedized military and aerospace FPGA platforms depend on PLCC-20 socketed PROMs for ease of factory programming and field updates. The EPC2LC20V's industrial -40C to +85C operating range meets most military ground and avionics thermal profiles, and its lead-free PLCC-20 package satisfies RoHS requirements for new programs. The on-chip DCLK oscillator removes the need for an external configuration clock source - valuable in low-BOM aerospace designs where every additional component is a reliability concern.
Recommended
FPGA Development Board Boot Loader
Altera/Intel FPGA development kits such as the Cyclone II Nios II and APEX 20K reference boards historically included an EPC2LC20V socket on the board for evaluation use. The PLCC-20 ZIF socket lets students and engineers swap bitstreams without soldering, and the JTAG interface lets the Altera USB-Blaster or ByteBlaster program the PROM directly. With 1.6 Mb Flash, the EPC2LC20V can store multiple demo projects including Nios II firmware + soft-core CPU bitstreams for the Cyclone II family.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20V — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LC20 | EPC2LC20NA | EPC1LC20 | EPC1441LC20 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Size | 1.6 Mb Flash | 1.6 Mb Flash | 1.6 Mb Flash | 1.6 Mb Flash | 0.4 Mb Flash (-75%) | 0.4 Mb OTP EPROM (-75%) |
| Technology | Flash (100k cycles) | Flash (100k cycles) | Flash (100k cycles) | Flash (100k cycles) | Flash (100k cycles) | OTP EPROM (one-time) |
| JTAG (IEEE 1149.1) | Yes (in-system programmable) | Yes (in-system programmable) | Yes (in-system programmable) | Yes (in-system programmable) | Yes (in-system programmable) | No (OTP only) |
| Configuration Modes | Passive Serial + 8-bit parallel | Passive Serial + 8-bit parallel | Passive Serial + 8-bit parallel | Passive Serial + 8-bit parallel | Passive Serial only | Passive Serial only |
| Max DCLK Frequency | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| Lead-Free / RoHS | Yes (V suffix, lead-free) | No (Sn/Pb finish) | No (Sn/Pb finish) | No (Sn/Pb finish) | No (Sn/Pb finish) | No (Sn/Pb finish) |
Key Differentiators
- Lead-free / RoHS compliant PLCC-20 package (vs EPC2LC20N)
- 4x the configuration memory of EPC1 family (vs EPC1LC20)
- 8-bit parallel configuration mode support (vs EPC1441LC20)
Design Notes
The EPC2LC20V operates from a single 3.3 V supply (3.0 V to 3.6 V) per the Altera datasheet. Place a 0.1 uF decoupling capacitor as close as possible to the VCC pin (pin 9) and a 10 uF bulk capacitor near the PLCC-20 socket to suppress the in-rush transient when the EPC2 begins driving DCLK into the FPGA. During JTAG programming, peak current can briefly reach ~30 mA; the bulk capacitor prevents the VCC rail from sagging.
Route DCLK and DATA[0] as a matched-length pair to the FPGA's DCLK and DATA0 inputs, keeping trace length under 50 mm to avoid ringing. For 8-bit parallel configuration, route DATA[0..7] as a byte-wide bus with matched lengths, and tie the EPC2 nCS pin to the FPGA's nCONFIG so configuration begins only after the FPGA is ready. Keep JTAG pins (TDI/TMS/TCK/TDO) in a dedicated daisy-chain segment so the EPC2 and target FPGA share the chain without stubs.
Do NOT connect the EPC2LC20V to the EPCS / EPCQ Active Serial (AS) interface of newer Altera/Intel FPGAs (Cyclone IV onward) - the EPC2 only supports Passive Serial (PS) and JTAG modes. Attempting AS-mode operation will leave the FPGA unconfigured. Also verify that the FPGA's bitstream fits within 1.6 Mb - if it does not, cascade a second EPC2 device using the nCE pin to expand the effective storage.
Compliance Information
Lead-free (V suffix) per Altera package designation. AEC-Q100 qualification not stated by manufacturer - not suitable for automotive safety-critical applications without further qualification. RoHS and REACH compliance inferred from lead-free package marking.
