EPC2LI20J vs EPC2LI20N Comparison
Detailed side-by-side comparison of EPC2LI20J by Altera and EPC2LI20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LI20J | EPC2LI20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $5.10 |
| Memory Type | In-System Programmable Configuration PROM (flash) | Non-volatile configuration PROM (Flash) |
| Memory Size | 1,695,680 bits (1.6Mb) | 1.6 Mbit |
| Organization | 65,536 x 1-bit (serial interface) | β |
| Interface | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | β |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | β |
| ISP Programming Interface | JTAG (IEEE 1149.1) | β |
| Cascade Support | Yes (multi-device configuration chain) | β |
| Internal Oscillator | Yes (configures without external clock source) | β |
| Package | 20-pin PLCC with J-leads (JEDEC MS-018) | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Configuration Clock (DCLK) | Up to 33 MHz | β |
| Programmable Type | β | In System Programmable (ISP via JTAG) |
| Configuration Mode | β | Serial |
| Maximum Configuration Frequency | β | 10 MHz |
| Supply Voltage (VCCIO) | β | 4.5 V to 5.5 V |
| Package / Case | β | 20-PLCC (J-Lead), 9x9 mm |
| Mounting Type | β | Surface Mount |
| Packaging | β | Tube |
| Supported FPGA Series | β | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | β | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | β | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |