EPC2LI20N - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
MPN: EPC2LI20N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.45 | $8.45 |
| 10 | $7.62 | $76.20 |
| 100 | $6.8 | $680.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.1 | $5,100.00 |
EPC2LI20N Overview
A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and serially shifts it into the FPGA during power-up or reconfiguration. The EPC2 belongs to the broader family of programmable read-only memory (PROM) -> serial configuration memory -> FPGA configuration devices -> memory ICs taxonomy. It uses a JTAG-driven in-system programmability model so designers can re-flash the configuration image on populated boards without removing the device, which dramatically simplifies field upgrades and debugging.
Key features include 1.6 Mbit Flash memory density, 20-pin PLCC (J-Lead) packaging, JTAG-based ISP, 3.0V/5.0V dual supply support, and a serial configuration clock rate up to 10 MHz. The device exposes standard Altera serial configuration signals (nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE) so it interfaces to legacy Altera FPGA configuration controllers without glue logic.
The EPC2LI20N uses a 4-pin serial interface to stream configuration data, with the FPGA acting as the configuration master. Internal oscillator and JTAG controller remove the need for external programming hardware, while in-system programming is supported via IEEE 1149.1 boundary scan. The result is a small-footprint, low-pin-count configuration solution that fits alongside the FPGA on the same PCB.
Typical applications include configuring Altera Cyclone series FPGAs in industrial controllers, Stratix II FPGAs in telecommunications line cards, and APEX II devices in DSP co-processing boards. It is also used in test and measurement equipment that requires field-updatable configuration.
When designing with this device, ensure the JTAG chain order is correct when multiple JTAG devices share the same TCK/TDI/TMS bus. The dual-supply design requires both 3.3V and 5V rails (or a single 3.3V rail with appropriate level shifting) to be present during configuration.
This page synthesizes distributor pricing, drop-in PLCC-20 alternatives from the Altera/Intel EPC family, and PCB-layout design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPC2LI20N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LI20N (same form factor and footprint) β differing in Memory Type, Mounting Type, Package, Supported FPGA Families, Interface.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2LC20N
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC2LI20
β Drop-Inβ In Stock
$5.95 / Unit
View Datasheet βEPC2LC22N
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPC1LC20N
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEPC2LC21N
β Drop-Inβ In Stock
$10.95 / Unit
View Datasheet βEPC2LI20N Maximum Ratings & Electrical Characteristics
| Memory Type | Non-volatile configuration PROM (Flash) |
| Memory Size | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) |
| Configuration Mode | Serial |
| Maximum Configuration Frequency | 10 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V |
| Package / Case | 20-PLCC (J-Lead), 9x9 mm |
| Mounting Type | Surface Mount |
| Packaging | Tube |
| Supported FPGA Series | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
EPC2LI20N Pin Configuration
| Pin 1 | DATA β Serial configuration data output to FPGA |
| Pin 2 | DCLK β Serial configuration clock from FPGA |
| Pin 3 | nCS β Chip select (active low) from FPGA |
| Pin 4 | nCONFIG β Configuration control (active low) |
| Pin 5 | nSTATUS β Configuration status (active low) |
| Pin 6 | CONF_DONE β Configuration complete (active high) |
| Pin 7 | TDI β JTAG test data in |
| Pin 8 | TMS β JTAG test mode select |
| Pin 9 | TCK β JTAG test clock |
| Pin 10 | TDO β JTAG test data out |
| Pin 11 | GND β Ground |
| Pin 12 | OE β Output enable (active low) |
| Pin 13 | VCCIO β I/O supply (4.5 V to 5.5 V) |
| Pin 14 | VCCINT β Core supply (3.0 V to 3.6 V) |
| Pin 15 | GND β Ground |
| Pin 16 | NC β Not connected (per datasheet) |
| Pin 17 | NC β Not connected (per datasheet) |
| Pin 18 | NC β Not connected (per datasheet) |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | NC β Not connected (per datasheet) |
Typical Applications
EPC2LI20N is suitable for 6 applications: Altera Cyclone FPGA Configuration, Stratix II Prototyping Boards, Industrial Motor Control Platforms, Telecommunications Line Cards, Test and Measurement Instrumentation, Legacy Board Repair and Field Service.
Altera Cyclone FPGA Configuration
The EPC2LI20N stores the configuration bitstream for Altera Cyclone series FPGAs (EP1C3, EP1C6, EP1C12, EP1C20) used in industrial control and DSP boards. The 1.6 Mbit density matches the bitstream size of EP1C3 through EP1C12 FPGAs; the 10 MHz serial configuration clock keeps FPGA initialization under 100 ms for these densities, and the JTAG ISP interface lets field engineers re-flash firmware without removing the device from the board.
Recommended
Stratix II Prototyping Boards
In Stratix II (EP2S15, EP2S30) prototyping platforms the EPC2LI20N serves as a secondary configuration source for debugging and field updates. Although larger Stratix II devices typically use EPC4/EPC8/EPC16, the EPC2LI20N is a cost-effective option for EP2S15-class designs where 1.6 Mbit is sufficient. The dual 3.3 V/5 V supply interface allows direct connection to the Stratix II configuration pins without level shifters, simplifying PCB layout.
Recommended
Industrial Motor Control Platforms
Variable-frequency drives and servo controllers built around Altera ACEX 1K or Cyclone FPGAs use the EPC2LI20N to store the field-oriented control (FOC) firmware bitstream. The industrial temperature grade (-40 C to +85 C) of the EPC2LI20N is well suited to factory-floor enclosures, and the JTAG ISP capability lets service technicians swap control algorithms without opening the drive cabinet. The 20-PLCC package is socket-compatible, simplifying field replacement.
Recommended
Telecommunications Line Cards
Legacy telecom line cards based on Altera APEX II (EP2A15, EP2A25) FPGAs use the EPC2LI20N as a compact serial configuration source. The 9x9 mm 20-PLCC footprint fits dense line-card PCB layouts where board area is at a premium, and the JTAG interface enables remote bitstream updates via the card management controller. The 5 V VCCIO tolerance allows direct connection to APEX II multi-voltage configuration banks without level translation.
Recommended
Test and Measurement Instrumentation
Oscilloscope, logic analyzer, and arbitrary waveform generator front-ends built on Altera Cyclone or Stratix II FPGAs use the EPC2LI20N to allow in-the-field firmware updates as new measurement algorithms are released. The JTAG ISP capability combined with 10 MHz serial configuration reduces product downtime during firmware upgrades, and the PLCC-20 socketable package simplifies board-level rework when the configuration PROM is replaced.
Recommended
Legacy Board Repair and Field Service
The EPC2LI20N remains in active service for repairing legacy Altera FPGA boards in aerospace, defense, and industrial automation systems where board redesign is not cost-effective. Authorized franchised inventory has been constrained since the part was declared obsolete, but a healthy broker supply chain through distributors such as Heisener, WIN SOURCE, and TrustedParts.com keeps spares available as of 2026-09-11. Engineers should verify date code and lot traceability when sourcing through brokers.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LI20N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LC20 | EPC2LI20 | EPC2LC22N | EPC1LC20N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Package | 20-PLCC (J-Lead) 9x9 mm | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 0.5 Mbit (EPC1 family) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Configuration Clock | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade for harsh environments (vs EPC2LC20N)
- 1.6 Mbit density matches Cyclone EP1C3-EP1C12 bitstreams (vs EPC1LC20N)
- JTAG ISP enables field firmware updates (vs EPC2LI20)
Design Notes
The EPC2LI20N requires both VCCINT (3.0-3.6 V) and VCCIO (4.5-5.5 V) rails to be present and stable before the FPGA begins configuration. Power-sequencing VCCIO before VCCINT is recommended to avoid latch-up; decouple each supply pin with a 100 nF ceramic capacitor placed within 5 mm of the package, plus a 10 uF bulk capacitor on the VCCINT rail. Estimated: based on typical dual-supply PROM decoupling guidelines from the Altera EPC2 datasheet.
Route the JTAG signals (TCK, TDI, TMS, TDO) as a daisy-chain when multiple JTAG devices share the bus. Keep trace lengths matched within 25 mm and place a 10 kohm pull-up on TCK, TDI, and TMS to VCCIO to define the logic state during FPGA configuration. The nCONFIG/nSTATUS/CONF_DONE handshake signals should be pulled up to VCCIO with 10 kohm resistors and routed away from switching power converter nodes to avoid false triggering during power-up.
Do not exceed 5.5 V on VCCIO or 3.6 V on VCCINT; transient overshoot during hot-plug events can permanently damage the Flash cells. When programming in-system via JTAG, ensure the FPGA is not simultaneously driving DCLK or DATA, otherwise bus contention will corrupt the bitstream. Finally, verify the JTAG chain order matches the BSDL file before issuing the first PROG command to avoid inadvertently programming the wrong device.
Compliance Information
RoHS and REACH compliance status not explicitly stated in the verified web data; refer to the Altera/Intel FPGA PCN archive for the official compliance certificate. Part is not AEC-Q100 qualified - this configuration PROM is intended for industrial/commercial FPGA configuration, not automotive safety applications.
