EPC2LI20PULLS vs EPC2LI20J Comparison
Detailed side-by-side comparison of EPC2LI20PULLS by Intel and EPC2LI20J by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2LI20PULLS
EPC2LI20PULLS - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
EPC2LI20PULLS ObsoleteSpecification Comparison
| Parameter | EPC2LI20PULLS | EPC2LI20J |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.75 |
| Memory Type | Serial Configuration Flash PROM | In-System Programmable Configuration PROM (flash) |
| Memory Size | 1.6 Mbit | 1,695,680 bits (1.6Mb) |
| Configuration Interface | Serial (Altera FPP / PS modes) | β |
| Maximum Clock Frequency | 10 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | β |
| I/O Tolerance | 5 V tolerant configuration pins | β |
| Programmability | In-system via IEEE 1149.1 JTAG | β |
| Compression Support | Yes (real-time decompression in target FPGA) | β |
| Multi-Device Cascade | Yes (daisy-chain supported) | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Package | 20-pin PLCC (J-Lead, 9x9 mm) | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Mounting Type | Surface Mount / Socket | β |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur | β |
| Organization | β | 65,536 x 1-bit (serial interface) |
| Interface | β | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | β | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | β | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | β | JTAG (IEEE 1149.1) |
| Cascade Support | β | Yes (multi-device configuration chain) |
| Internal Oscillator | β | Yes (configures without external clock source) |
| Programming Cycles | β | [DATA_NEEDED: minimum endurance cycles] |
| Configuration Clock (DCLK) | β | Up to 33 MHz |