EPC2LI20PULLS - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
MPN: EPC2LI20PULLS ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPC2LI20PULLS Overview
A configuration PROM is a non-volatile serial-flash memory whose sole purpose is to load bitstream data into an SRAM-based FPGA every time the system powers up or whenever a reconfiguration is required. Because SRAM FPGAs lose their configuration on power-down, a boot memory is required. EPC-series PROMs are part of the Altera enhanced configuration family that supports multi-device cascade chains, real-time decompression (which effectively multiplies storage density by 2x in typical workloads), and 8-/16-bit data-width modes for higher throughput on larger FPGAs.
Key technical features of the EPC2LI20 include a 10 MHz maximum configuration clock rate, a 3.3 V core supply with 5 V tolerant I/O on configuration pins, in-system programmability through an IEEE 1149.1 JTAG interface, and built-in error-checking circuitry that aborts configuration if any bitstream error is detected. The device supports daisy-chained programming of multiple PROMs so a single JTAG link can program a chain of configuration devices on the board. Unused flash regions are also accessible by a Nios processor or other PLD for general-purpose non-volatile storage.
Typical applications include FPGA configuration bitstream storage for Altera/Intel Cyclone, Stratix, APEX, ACEX, Mercury, and Excalibur FPGA families, JTAG-programmable production line bitstream loading, multi-board systems where configuration data must cascade between FPGAs, and embedded designs that reuse spare flash space for firmware or user data. The PLCC-20 footprint is the JEDEC-standard 20-lead plastic-leaded chip-carrier, suitable for socketed or surface-mount assembly and compatible with legacy Altera reference designs.
When designing with EPC2LI20PULLS, ensure that the JTAG chain order matches the schematic, leave nCONFIG/nSTATUS lines properly pulled, and verify that the configuration bitstream is generated for the EPC2's compression mode. Engineers targeting newer Intel Cyclone 10 or Stratix 10 devices should instead use the EPCQ-series or the on-chip configuration subsystem of modern FPGAs, since the EPC2 is intended for legacy SRAM-based LUT families.
Drop-in alternatives for EPC2LI20PULLS — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LI20PULLS (same form factor and footprint) — differing in Memory Type, Mounting Type, Package, Memory Size, Configuration Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LI20
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPC2LI20J
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPC2LI20NGA
✅ Drop-In✓ In Stock
$4.35 / Unit
View Datasheet →EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC2LI20PULLS Maximum Ratings & Electrical Characteristics
| Memory Type | Serial Configuration Flash PROM |
| Memory Size | 1.6 Mbit |
| Configuration Interface | Serial (Altera FPP / PS modes) |
| Maximum Clock Frequency | 10 MHz |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Tolerance | 5 V tolerant configuration pins |
| Programmability | In-system via IEEE 1149.1 JTAG |
| Compression Support | Yes (real-time decompression in target FPGA) |
| Multi-Device Cascade | Yes (daisy-chain supported) |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 20-pin PLCC (J-Lead, 9x9 mm) |
| Mounting Type | Surface Mount / Socket |
| MSL Level | 3 (168 hours) |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur |
EPC2LI20PULLS Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA or external source |
| Pin 3 | nCONFIG — Configuration control (active-low reset/request) |
| Pin 4 | nSTATUS — Configuration status output (active-low error flag) |
| Pin 5 | nCS — Chip select input (active-low) |
| Pin 6 | nCE — Chip enable input (active-low, for cascade chain) |
| Pin 7 | OE — Output enable (active-low, gates DATA output) |
| Pin 8 | VCC — 3.3 V core supply |
| Pin 9 | GND — Ground reference |
| Pin 10 | TMS — JTAG test mode select |
| Pin 11 | TCK — JTAG test clock |
| Pin 12 | TDO — JTAG test data output |
| Pin 13 | TDI — JTAG test data input |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
Typical Applications
EPC2LI20PULLS is suitable for 6 applications: Legacy Cyclone FPGA Boot Memory, APEX 20K Multi-Device Configuration, Stratix GX Reference Design Boot, Industrial Control Board Configuration, JTAG Factory Programming Station, Reconfigurable Compute Platform.
Legacy Cyclone FPGA Boot Memory
The EPC2LI20PULLS provides the non-volatile 1.6 Mbit boot storage required by Altera Cyclone (EP1C3/EP1C6/EP1C12) and Cyclone II FPGAs, whose SRAM-based LUT fabric loses configuration on every power-down. The PROM's 10 MHz DCLK comfortably clocks the passive-serial (PS) configuration mode of these FPGAs in tens of milliseconds. With real-time decompression, the 1.6 Mbit density actually stores up to ~3 Mbit of compressed bitstream, covering the largest Cyclone II designs. Placed adjacent to the FPGA with nCONFIG/nSTATUS pulled high through 10 kohm resistors, the EPC2LI20PULLS enables single-chip boot without external processor intervention. Recommended companions: EP1C6Q240C8 FPGA, EPC2JTAG programmer.
Recommended
APEX 20K Multi-Device Configuration
For APEX 20K and APEX II FPGA designs where one board hosts multiple FPGAs, the EPC2LI20PULLS supports daisy-chained configuration mode, allowing several PROMs to cascade via nCS/nCE handshaking. Each EPC2LI20PULLS holds the bitstream for one APEX device in the chain, and the JTAG link programs them all in one factory operation. The 3.3 V supply and 5 V tolerant configuration pins simplify mixed-voltage board designs. With 1.6 Mbit density the PROM supports APEX 20K200 and 20K400 devices in compressed mode. Recommended companions: EP20K200EQC240 APEX FPGA, JTAG programmer for chain programming.
Recommended
Stratix GX Reference Design Boot
In Stratix GX (EP1SGX10/25/40) telecommunications designs the EPC2LI20PULLS provides factory-loaded bitstream storage with the bandwidth to support the larger configuration files of these high-density FPGAs. The 10 MHz DCLK keeps total configuration time under 200 ms even for the largest Stratix GX bitstreams compressed into the 1.6 Mbit space. Its JTAG programmability allows field updates via the JTAG chain alongside the Stratix GX itself. The PLCC-20 package supports socketed assembly for serviceability in carrier-grade telecom hardware. Recommended companions: EP1SGX25FF1020C5N Stratix GX FPGA, EPC2LC20N alternate.
Recommended
Industrial Control Board Configuration
For industrial PLC, motor-control, and SCADA boards using ACEX 1K or APEX 20KE FPGAs, the EPC2LI20PULLS provides reliable factory-loaded configuration storage across -40C to +85C industrial temperature range. The PLCC-20 socketed package allows field replacement of PROMs to update firmware without reworking the FPGA, an important feature for installed industrial hardware. The 3.3 V operation matches typical industrial 3.3 V rails generated from 24 V backplane supplies. Combined with watchdog and nSTATUS error-checking, the EPC2LI20PULLS ensures deterministic boot in factory-automation environments. Recommended companions: EP1K10QC208 ACEX FPGA, 24V-to-3.3V DC-DC converter.
Recommended
JTAG Factory Programming Station
Production-line JTAG programming stations use EPC2LI20PULLS as the target device when pre-loading Altera bitstreams onto PLCC-20 sockets before SMT placement. The in-system programmability via IEEE 1149.1 JTAG means the same fixture can program any EPC2 family device, and daisy-chaining allows multiple boards to be programmed in parallel for high-volume manufacturing. The factory tape-and-reel packaging (PULLS suffix) suits pick-and-place SMT lines after pre-programming. Combined with Altera's ByteBlasterMV or USB-Blaster programmer, the EPC2LI20PULLS enables fast, reliable factory firmware load. Recommended companions: ByteBlasterMV programmer, JTAG chain header.
Recommended
Reconfigurable Compute Platform
In reconfigurable computing platforms where a Nios soft-core processor or external controller requests on-the-fly FPGA reconfiguration, the EPC2LI20PULLS stores multiple compressed bitstreams that the FPGA can switch between via nCONFIG pulses. The 1.6 Mbit density holds several partial-reconfiguration contexts for compute-acceleration workloads such as DSP or cryptographic pipelines. The unused flash regions of the EPC2LI20PULLS are accessible by a Nios processor for general-purpose non-volatile storage, doubling as firmware memory for the embedded system. This dual-purpose use reduces total BOM cost on space-constrained compute boards. Recommended companions: Nios II soft-core, EP2C35 Cyclone II FPGA.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LI20PULLS — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LI20N | EPC2LI20 | EPC2LI20J | EPC2LI20NGA | EPC1LC20 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) - same brand | Intel (formerly Altera) - same brand | Intel (formerly Altera) - same brand | Intel (formerly Altera) - same brand | Intel (formerly Altera) - same brand |
| Package | 20-pin PLCC (J-Lead) | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same | 20-pin PLCC - same |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | ~0.5 Mbit (smaller) |
| Real-Time Decompression | Yes | Yes | Yes | Yes | Yes | No (EPC1 family) |
| Maximum Clock Frequency | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| Supply Voltage | 3.0 V to 3.6 V (3.3 V typ) | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| JTAG Programmability | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | 0C to +70C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty 1) | $18.50 | $17-22 | $15-20 | $17-22 | $18-24 | $10-15 |
Key Differentiators
- Factory tape-and-reel variant for SMT production lines (vs EPC2LI20N (tube packaging variant))
- 1.6 Mbit density with real-time decompression (vs EPC1LC20)
- Industrial temperature range (-40C to +85C) (vs EPC2LC20 (commercial temperature))
Design Notes
Place the EPC2LI20PULLS as close as possible to the target FPGA's configuration pins (DATA, DCLK, nCONFIG, nSTATUS) to minimize trace length and avoid signal-integrity issues at the 10 MHz configuration clock. Keep the configuration traces away from switching power supply nets and high-speed signal traces. Add a 10 kohm pull-up on nCONFIG and nSTATUS per Altera reference design, and use a 100 nF decoupling capacitor on the VCC pin placed within 5 mm of the package.
Do not connect JTAG signals (TMS/TCK/TDO/TDI) to anything other than the JTAG chain header or the FPGA's JTAG pins - mixing JTAG chains between the EPC2 and FPGA without proper buffering can cause programming failures. Verify that the Quartus programmer flow targets the correct device ID in mixed JTAG chains, and that nCE is tied correctly in single-device configurations (typically tied to GND with the nCS used for cascade).
The 20-pin PLCC socket should be a low-profile through-hole or surface-mount type with proper land pattern per JEDEC PLCC-20 standard. For socketed designs, consider a machined-pin socket for reliable field replacement in industrial environments. Reserve PCB area around the PLCC for a programming clip access if factory JTAG pre-programming is used, and add test points on DATA and DCLK for oscilloscope verification during bring-up.
Compliance Information
Compliance status not explicitly stated in verified data; original Altera EPC2 family parts were typically offered in both SnPb and Pb-free variants depending on order code. RoHS, lead-free, and halogen-free status should be verified with the distributor at time of order for production hardware.
