EPC2T32U-CAF48 vs EPC2LI20N Comparison
Detailed side-by-side comparison of EPC2T32U-CAF48 by Altera and EPC2LI20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC2T32U-CAF48 - Altera/Intel 2Mb Config Device, 8MHz, 48-QFN | XAIPART
EPC2T32U-CAF48 β Last Time Buy
Specification Comparison
| Parameter | EPC2T32U-CAF48 | EPC2LI20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.60 | $5.10 |
| Memory Type | Non-volatile flash configuration memory | Non-volatile configuration PROM (Flash) |
| Memory Density | 2 Mb (2097152 bits) | β |
| Configuration Interface | Altera FPP (8-bit) / PS (4-wire) / AS (serial) | β |
| Maximum Configuration Clock (DCLK) | 8 MHz | β |
| Supply Voltage (VCC) | 3.3 V (typical) | β |
| I/O Tolerance | 5 V tolerant | β |
| Program/Erase Endurance | 10,000 cycles per sector minimum | β |
| Data Retention | 20 years minimum | β |
| Programming Interface | IEEE 1149.1 (JTAG) / IEEE 1532 | β |
| Package | 48-pin QFN (CAF suffix) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40 C to +85 C (industrial grade, "U") | [DATA_NEEDED: operating temperature range] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Lead-Free Finish | Yes (CAF suffix indicates lead-free) | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Supported FPGA Families | Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K, Mercury, Excalibur | β |
| Memory Size | β | 1.6 Mbit |
| Programmable Type | β | In System Programmable (ISP via JTAG) |
| Configuration Mode | β | Serial |
| Maximum Configuration Frequency | β | 10 MHz |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | β | 4.5 V to 5.5 V |
| Package / Case | β | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | β | Tube |
| Supported FPGA Series | β | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | β | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | β | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |