EPC4SI8N-JHG2 vs EPC2LI20N Comparison

Detailed side-by-side comparison of EPC4SI8N-JHG2 by Altera and EPC2LI20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC4SI8N-JHG2 EPC2LI20N
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.15 $5.10
Memory Type Flash configuration PROM Non-volatile configuration PROM (Flash)
Memory Density 4 Mbit β€”
Interface Serial (active serial, AS) β€”
Max Serial Clock 40 MHz β€”
Package 8-SOIC (SOIC-8) β€”
Pin Count 8 β€”
Programmability In-system programmable via JTAG (IEEE 1149.1) β€”
JTAG Support Yes (ISP via JTAG) β€”
Cascadable No β€”
Operating Supply Voltage 3.3 V typical (refer to datasheet) β€”
Supported FPGA Families Stratix, Cyclone, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K β€”
Configuration Mode Active Serial (AS) Serial
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Memory Size β€” 1.6 Mbit
Programmable Type β€” In System Programmable (ISP via JTAG)
Maximum Configuration Frequency β€” 10 MHz
Supply Voltage (VCCINT) β€” 3.0 V to 3.6 V
Supply Voltage (VCCIO) β€” 4.5 V to 5.5 V
Package / Case β€” 20-PLCC (J-Lead), 9x9 mm
Packaging β€” Tube
Supported FPGA Series β€” ACEX 1K, APEX II, Cyclone, Stratix II
JTAG Interface β€” IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO)
Configuration Pins β€” nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE

Datasheets & Resources

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