EPC8820ARC208-3 vs EPC16UC88 Comparison
Detailed side-by-side comparison of EPC8820ARC208-3 by Altera and EPC16UC88 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC8820ARC208-3
EPC8820ARC208-3 - Altera Enhanced Config Device | 208-FQFP
EPC8820ARC208-3 ObsoleteSpecification Comparison
| Parameter | EPC8820ARC208-3 | EPC16UC88 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Obsolete | Unknown |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.10 | $0.00 |
| Device Type | Enhanced Configuration Device (EPC) | In-system programmable configuration PROM for FPGAs |
| Manufacturer | Altera (now Intel FPGA) | β |
| Configured Device Family | FLEX 8000, APEX 20K series (SRAM-based LUT) | β |
| Package | 208-FQFP (Plastic Quad Flat Pack) with Exposed Pad | 88-UBGA (11x8) |
| Terminal Form | Gull Wing | β |
| Number of Terminals | 208 | β |
| Package Shape | Square | β |
| Temperature Grade | Commercial | β |
| Mounting Type | Surface Mount | Surface mount |
| Configuration Interface | Altera passive serial (PS) configuration | β |
| Programming Method | JTAG / in-system programmable | β |
| Cascade Support | Yes (multi-device daisy-chain) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | β |
| Configuration Memory Capacity | β | 16 Mb |
| Supply Voltage | β | 3.3 V core and I/O |
| Package Family | β | UBGA |
| In-System Programmability | β | IEEE Std. 1532 compatible |
| Programming Language Support | β | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | β | Supported |
| nINIT_CONF Function | β | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | β | Configuration controller and flash memory |
| FPGA Configuration Use | β | Automatic configuration after power-up or system initialization |
| Data Output | β | Configuration data output controlled by OE and nCS |
| Output Control | β | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | β | 11 mm x 8 mm |
| REACH Status | β | [DATA_NEEDED: REACH status] |
| Operating Temperature | β | [DATA_NEEDED: operating temperature] |
| Output Current | β | [DATA_NEEDED: output current] |
| Configuration Frequency | β | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | β | [DATA_NEEDED: AEC-Q100 qualification] |