EPF10K130EBC356-1N vs EPF10K130EBC356-3 Comparison

Detailed side-by-side comparison of EPF10K130EBC356-1N by Altera and EPF10K130EBC356-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPF10K130EBC356-1N EPF10K130EBC356-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.20 $35.20
Family FLEX 10KE FLEX-10KE
Typical Gates 130,000 130,000
Maximum System Gates [DATA_NEEDED: maximum system gates for EPF10K130E] β€”
Logic Elements (LEs) 6,656 β€”
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count for EPF10K130E] 12
Total RAM Bits 65,536 24,576 bits (12 EABs Γ— 2 Kbit)
User I/O Pins 274 β€”
Package 356-LBGA 356-LBGA (35x35 mm)
Package Code LBGA β€”
Logic Family CMOS CMOS
Process Technology 0.22 Β΅m 0.22 Β΅m SRAM-based CMOS
Core Supply Voltage 2.5 V 2.375 V to 2.625 V
I/O Supply Voltage 3.3 V 2.5 V / 3.3 V / 5.0 V (multiVolt I/O)
Speed Grade -1 -3 (fastest)
Propagation Delay 0.6 ns β€”
Maximum Internal Frequency 333.33 MHz β€”
Operating Temperature 0 Β°C to 70 Β°C (Commercial) 0 Β°C to +70 Β°C (Commercial)
JTAG Boundary-Scan IEEE Std. 1149.1-1990 compliant β€”
PCI Compliance PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N] Non-compliant (SnPb ball finish on legacy BGA)
Series β€” FLEX-10KE
Logic Elements β€” 8,192
Logic Array Blocks (LABs) β€” 832
Maximum User I/Os β€” 274
Pin-to-Pin Propagation Delay (-3 grade) β€” 0.6 ns
Configuration Method β€” SRAM-based, JTAG (IEEE 1149.1) in-system programmable
Lead-Free β€” No
Lifecycle β€” Obsolete β€” last-time-buy / Rochester Electronics stock only

Datasheets & Resources

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