EPF10K200EFC672-2 vs EPF10K200SFC672-2 Comparison

Detailed side-by-side comparison of EPF10K200EFC672-2 by Intel and EPF10K200SFC672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPF10K200EFC672-2 EPF10K200SFC672-2
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $210.00 $320.00
Family FLEX 10KE β€”
Logic Elements 9,984 9,984
Typical Gates 200,000 β€”
Maximum User I/Os 470 β€”
Embedded Memory 98,304 bits β€”
Embedded Array Blocks (EABs) 12 β€”
Logic Array Blocks (LABs) 624 1,248
Package 672-BBGA (FineLine BGA) 672-pin FineLine BGA (FBGA), 45 Γ— 45 mm, 1.27 mm pitch
Package Dimensions 45 x 45 mm β€”
Ball Pitch 1.27 mm β€”
Process Technology 0.22 um CMOS 0.22 Β΅m CMOS
Speed Grade -2 -2
Propagation Delay 0.4 ns β€”
Operating Temperature 0 C to 70 C 0 Β°C to +70 Β°C (Commercial)
Supply Voltage (Core) [DATA_NEEDED: core Vcc] β€”
Programmability JTAG (IEEE 1149.1) / in-system β€”
RoHS Status Compliant (per distributor listing) [DATA_NEEDED: RoHS compliance status]
Logic Family CMOS β€”
Series β€” FLEX 10KE
System Gates β€” 200,000
User I/O Pins β€” 470
Embedded Memory (bits) β€” 98,304
Core Supply Voltage β€” 2.5 V (2.375 V to 2.625 V)
I/O Supply Voltage β€” MultiVolt 2.5 V / 3.3 V / 5.0 V
Internal Propagation Delay β€” 0.4 ns
Maximum Operating Frequency β€” 200 MHz
Configuration Method β€” SRAM-based, passive parallel asynchronous
Boundary Scan β€” IEEE 1149.1 (JTAG)
On-chip PLL β€” Yes

Datasheets & Resources

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