EPF10K200SBC356-1 vs EPF10K200SBC356-2 Comparison
Detailed side-by-side comparison of EPF10K200SBC356-1 by Intel and EPF10K200SBC356-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPF10K200SBC356-1 - 200K FLEX 10K FPGA, 274 I/O, 356-BGA | Intel / Altera
EPF10K200SBC356-1 NrndSpecification Comparison
| Parameter | EPF10K200SBC356-1 | EPF10K200SBC356-2 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $580.00 | $178.00 |
| Family | FLEX 10K (Classic embedded array) | FLEX 10KS (Embedded Programmable Logic) |
| Logic Elements / Cells | 9,984 | 9984 |
| Number of LABs / CLBs | 1,248 | β |
| Total RAM Bits | 98,304 | β |
| Equivalent Gate Count | 200,000 (system gates ~513,000) | β |
| Number of User I/Os | 274 | β |
| Propagation Delay | 0.4 ns (-1 speed grade) | 0.4 ns (per datasheet) |
| Core Supply Voltage | 2.375 V to 2.625 V | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | 0C to +70C (Commercial) |
| Package | 356-LBGA (35 x 35 mm, 1.27 mm pitch) | 356-LBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Family / Process | CMOS SRAM LUT | β |
| Configuration Method | SRAM (volatile) - requires configuration device or JTAG | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (legacy part) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Series | β | FLEX 10KS |
| Logic Array Blocks (LABs) | β | 1248 |
| Embedded Memory Bits (EAB) | β | 98304 |
| System Gates | β | 200,000 |
| User I/Os | β | 274 |
| Number of I/O Banks | β | 8 |
| Supply Voltage (Core) | β | 2.5 V (2.375 V - 2.625 V) |
| I/O Voltage (PCI-compatible) | β | 3.3 V / 5.0 V tolerant |
| Process Technology | β | 0.22 um CMOS |
| Speed Grade | β | -2 |
| Configuration | β | SRAM-based (volatile, requires configuration device) |
| Boundary Scan | β | Yes (JTAG IEEE 1149.1) |
| PLL | β | Yes (on-chip) |