EPF10K200SFC672-1 vs EPF10K200SFC672-2 Comparison
Detailed side-by-side comparison of EPF10K200SFC672-1 by Altera and EPF10K200SFC672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPF10K200SFC672-1 | EPF10K200SFC672-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $138.75 | $320.00 |
| Series | FLEX 10KE | FLEX 10KE |
| Family | FLEX 10KE (FLEX-10KS) | β |
| Logic Elements / Cells | 9984 | β |
| Total RAM Bits | 98304 | β |
| Number of LABs/CLBs | 1248 | β |
| Number of User I/Os | 470 | β |
| Number of Gates | 200K system gates | β |
| Core Voltage (VCCINT) | 2.5 V | β |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt) | β |
| Maximum Operating Frequency | 250 MHz | 200 MHz |
| Propagation Delay | 0.4 ns | β |
| Process Technology | 0.22 Β΅m CMOS, SRAM-based | 0.22 Β΅m CMOS |
| Package Type | 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | β |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) | 0 Β°C to +70 Β°C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) + serial/parallel passive configuration | β |
| Embedded Array Blocks (EABs) | 12 | β |
| Speed Grade | -1 | -2 |
| Mounting Type | Surface Mount | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | β | 9,984 |
| System Gates | β | 200,000 |
| Logic Array Blocks (LABs) | β | 1,248 |
| User I/O Pins | β | 470 |
| Embedded Memory (bits) | β | 98,304 |
| Core Supply Voltage | β | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | β | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Propagation Delay | β | 0.4 ns |
| Package | β | 672-pin FineLine BGA (FBGA), 45 Γ 45 mm, 1.27 mm pitch |
| Configuration Method | β | SRAM-based, passive parallel asynchronous |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |
| On-chip PLL | β | Yes |