EPF10K200SFC672-2 vs EPF10K200SFI672-2 Comparison

Detailed side-by-side comparison of EPF10K200SFC672-2 by Altera and EPF10K200SFI672-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPF10K200SFC672-2 EPF10K200SFI672-2
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $320.00 $99.50
Series FLEX 10KE β€”
Logic Elements 9,984 9984
System Gates 200,000 200000
Logic Array Blocks (LABs) 1,248 1248
User I/O Pins 470 β€”
Embedded Memory (bits) 98,304 β€”
Process Technology 0.22 Β΅m CMOS 0.22 Β΅m (Arrow lists 0.42 Β΅m)
Core Supply Voltage 2.5 V (2.375 V to 2.625 V) 2.5 V
I/O Supply Voltage MultiVolt 2.5 V / 3.3 V / 5.0 V β€”
Speed Grade -2 -2
Internal Propagation Delay 0.4 ns β€”
Maximum Operating Frequency 200 MHz β€”
Package 672-pin FineLine BGA (FBGA), 45 Γ— 45 mm, 1.27 mm pitch 672-pin FineLine BGA (FBGA)
Operating Temperature 0 Β°C to +70 Β°C (Commercial) Industrial (-40C to +85C)
Configuration Method SRAM-based, passive parallel asynchronous β€”
Boundary Scan IEEE 1149.1 (JTAG) β€”
On-chip PLL Yes β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] Not compliant (per Arrow EU RoHS listing)
Family β€” FLEX 10KE
User I/Os β€” 470
Embedded Array Blocks (EABs) β€” 24
Embedded Memory (EAB SRAM) β€” 96 Kbit
Distributed Memory β€” 98304 bits
JTAG Boundary Scan β€” IEEE Std. 1149.1-1990 compliant
PCI Compliance β€” PCI Local Bus Specification Rev 2.2 (3.3 V, 33/66 MHz) on -1 speed grade
Programming β€” SRAM-based, in-system programmable

Datasheets & Resources

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