EPF6024ATC144-10N vs EPF6024ATC144-13 Comparison
Detailed side-by-side comparison of EPF6024ATC144-10N by Altera and EPF6024ATC144-13 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPF6024ATC144-10N
EPF6024ATC144-10N - FLEX 6000 FPGA 1960 LE 117 I/O TQFP-144 | Altera
EPF6024ATC144-10N ObsoleteAltera
EPF6024ATC144-13
EPF6024ATC144-13 - FLEX 6000 FPGA 24K Gates, 144-LQFP | Altera
EPF6024ATC144-13 ObsoleteSpecification Comparison
| Parameter | EPF6024ATC144-10N | EPF6024ATC144-13 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.95 | $7.10 |
| Family | FLEX 6000 | FLEX 6000 |
| Series | EPF6024A | β |
| Logic Elements (LEs) | 1960 | β |
| Logic Array Blocks (LABs) | 196 | 196 |
| Maximum User I/Os | 117 | β |
| Package | 144-pin TQFP (T144) | 144-pin LQFP (TQFP) |
| Pin/Pin-to-Pin Delay | -10 speed grade (10 ns class) | β |
| Process Technology | 5 V CMOS, SRAM-based | 0.42 Β΅m CMOS |
| Configuration Method | Serial or parallel, external memory | β |
| Core Supply Voltage (VCCINT) | 5.0 V | β |
| I/O Bank Voltages | 5.0 V / 3.3 V / 2.5 V compatible | β |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | β |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (commercial/industrial) |
| Lead-Free (Pb-Free) | Yes (suffix N) | β |
| RoHS Status | Compliant (per modern distributor listings) | unknown |
| Typical Gates | β | 24,000 |
| Logic Elements / Cells | β | 1,960 |
| Maximum User I/O | β | 117 |
| Mounting Type | β | Surface Mount |
| Core Supply Voltage | β | 3.3 V |
| I/O Supply Voltage | β | 3.3 V (5 V tolerant I/O) |
| Speed Grade | β | -13 (β13 ns pin-to-pin delay) |
| Maximum Internal Frequency | β | 142.86 MHz |
| Programmable Logic Type | β | SRAM-based FPGA, in-system programmable |
| Configuration Interface | β | Serial EPROM (EPC1/EPC2) and JTAG |
| Architecture | β | 4-input LUT-based LE with carry chain and EAB memory blocks |