Altera

EPF6024ATC144-10N - FLEX 6000 FPGA 1960 LE 117 I/O TQFP-144 | Altera

MPN: EPF6024ATC144-10N ✗ End of Life

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5.0 V Vdss 144-pin TQFP (T144) Package

From $14.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$28.5	$28.50
10	$24.75	$247.50
100	$20.1	$2,010.00
500	$17.4	$8,700.00
1,000	$14.95	$14,950.00

ℹ️ All prices are in USD

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EPF6024ATC144-10N Overview

The Altera (now Intel) EPF6024ATC144-10N is a member of the FLEX 6000 family of SRAM-based Field-Programmable Gate Arrays, providing 1960 logic elements organized as 196 Logic Array Blocks (LABs), 117 user I/O pins, and housed in a 144-pin TQFP (T144) plastic package with a speed grade of -10 (10 ns pin-to-pin delay class). It is fabricated on a 5 V CMOS process with on-chip flash/EPROM configuration support and operates over the commercial 0 C to +70 C junction range.

A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit built around an array of configurable logic blocks (CLBs or LABs), programmable interconnect, and I/O cells that the user can define after manufacturing. The FLEX 6000 family sits in Altera's older programmable-logic hierarchy between the classic MAX series and the high-density FLEX 10K/Stratix lines, targeting glue-logic replacement, bus interface bridging, and small-to-medium state-machine consolidation. As a programmable logic device (PLD) family, the EPF6024ATC144-10N belongs to the broader semiconductor category of logic ICs.

Key features include 1960 logic elements, 117 user I/O pins, built-in cascade and carry chains for high-speed arithmetic and wide-input functions, JTAG-based boundary-scan testability, and multi-voltage I/O support allowing mixed 5.0 V / 3.3 V / 2.5 V interface levels. The -10N suffix indicates a -10 speed grade and lead-free (Pb-free) assembly, with the trailing N denoting industrial-temperature material set in some supplier catalogs.

The architecture combines four-input look-up tables (LUTs), dedicated carry chains for fast adders and counters, and cascade chains for wide fan-in functions such as equality comparators. Each LAB contains 10 logic elements (LEs), and dedicated row/column interconnect minimizes routing delay. Embedded SRAM is not part of the FLEX 6000 family, distinguishing it from FLEX 10K; configuration is loaded from external EPROM, flash, or controller over a serial or parallel interface.

Typical applications include bus-interface bridges (e.g., ISA-to-PCI glue logic), peripheral controllers in industrial embedded boards, custom state machines in legacy telecom equipment, prototype ASIC replacement, and parallel I/O expansion for legacy microprocessors. The 144-pin TQFP package is footprint-compatible across the EPF6024ATC144 speed-grade family (-3, -1, -10), enabling drop-in PCB reuse when migrating between speed grades.

When designing with this device, plan for an external configuration memory (serial EEPROM or parallel EPROM) because the FLEX 6000 family is SRAM-based and loses its bitstream on power-down. Observe the 5.0 V core supply requirement (VCCINT), use decoupling per the datasheet's reference design, and verify I/O bank voltages against your bus partner before PCB layout.

This page consolidates drop-in speed-grade alternatives, parametric comparisons, and practical design considerations not always gathered in the original Altera datasheet.

Drop-in alternatives for EPF6024ATC144-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6024ATC144-10N (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Speed Grade, Configuration Memory.

EPF6024ATC144

Altera

Package: 144-pin LQFP

Process Technology: 0.42 µm CMOS

Configuration Memory: SRAM-based (volatile)