EPF6024ATC144-13 vs EPF6024ATC144-17 Comparison
Detailed side-by-side comparison of EPF6024ATC144-13 by Altera and EPF6024ATC144-17 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPF6024ATC144-13
EPF6024ATC144-13 - FLEX 6000 FPGA 24K Gates, 144-LQFP | Altera
EPF6024ATC144-13 ObsoleteIntel
EPF6024ATC144-17
EPF6024ATC144-17 - FLEX 6000 FPGA 117 I/O 144-TQFP | Intel
EPF6024ATC144-17 ObsoleteSpecification Comparison
| Parameter | EPF6024ATC144-13 | EPF6024ATC144-17 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $9.75 |
| Family | FLEX 6000 | FLEX 6000 |
| Process Technology | 0.42 Β΅m CMOS | β |
| Typical Gates | 24,000 | β |
| Logic Elements / Cells | 1,960 | β |
| Logic Array Blocks (LABs) | 196 | 196 |
| Maximum User I/O | 117 | β |
| Package | 144-pin LQFP (TQFP) | 144-pin TQFP (TQFP-144) |
| Mounting Type | Surface Mount | Surface Mount |
| Core Supply Voltage | 3.3 V | β |
| I/O Supply Voltage | 3.3 V (5 V tolerant I/O) | β |
| Speed Grade | -13 (β13 ns pin-to-pin delay) | -17 |
| Maximum Internal Frequency | 142.86 MHz | β |
| Programmable Logic Type | SRAM-based FPGA, in-system programmable | β |
| Configuration Interface | Serial EPROM (EPC1/EPC2) and JTAG | β |
| Operating Temperature | -40C to +85C (commercial/industrial) | Commercial (0C to +70C junction) |
| Architecture | 4-input LUT-based LE with carry chain and EAB memory blocks | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Logic Elements | β | 1960 |
| User I/O Pins | β | 117 |
| Configuration Memory | β | SRAM (volatile) |
| Core Voltage | β | 3.3 V |
| I/O Voltage Support | β | 1.8 V / 2.5 V / 3.3 V / 5.0 V PCI-compatible |
| Logic Element Structure | β | 4-input LUT + flip-flop |
| LEs per LAB | β | 10 |
| Configuration Modes | β | Passive Serial, Passive Parallel Async, JTAG |
| Boundary Scan | β | IEEE 1149.1 JTAG compliant |
| MSL Level | β | [DATA_NEEDED: MSL rating] |