EPF8820ATC144-11 vs EPF8820ATC144-15 Comparison
Detailed side-by-side comparison of EPF8820ATC144-11 by Altera and EPF8820ATC144-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPF8820ATC144-11
EPF8820ATC144-11 - FLEX 8000 FPGA 8K Gates 144-TQFP | Altera
EPF8820ATC144-11 ObsoleteAltera
EPF8820ATC144-15
EPF8820ATC144-15 - FLEX 8000 FPGA 8K Gates 672 Cells | Altera
EPF8820ATC144-15 NrndSpecification Comparison
| Parameter | EPF8820ATC144-11 | EPF8820ATC144-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.10 | $19.50 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 8,000 | 8000 |
| Logic Cells / Elements | 672 | β |
| Maximum User I/O | 112 | 112 |
| Package | 144-pin TQFP (Plastic Thin Quad Flat Pack) | 144-pin TQFP (also marketed as LQFP) |
| Package Dimensions | 20 mm x 20 mm, 0.5 mm pitch | β |
| Supply Voltage (Core) | 5.0 V nominal | 5 V |
| I/O Voltage (MultiVolt) | 3.3 V or 5.0 V | β |
| Process Technology | 0.42 um CMOS SRAM | 5 V CMOS SRAM |
| Internal Operating Frequency | up to 125 MHz | β |
| Configuration Method | Serial / Parallel EPROM, Altera EPC1/EPC1213/EPC1064/EPC1441, JTAG | Serial or parallel EPROM, JTAG |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to 70 C (commercial) |
| In-Circuit Reconfigurability | Yes (ICR) | Yes (ICR via external controller) |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | β |
| Speed Grade | -11 | -15 (approx. 15 ns tpd) |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Lead-free / RoHS Compliant (per distributor listing) | Lead-free / RoHS compliant (per distributor data) |
| Logic Elements (Cells) | β | 672 |
| I/O Voltage Support | β | 3.3 V or 5.0 V (MultiVolt I/O) |
| Configuration Devices | β | EPC1, EPC1064, EPC1213, EPC1441 |
| JTAG Support | β | Yes (IEEE 1149.1 boundary scan) |
| Architecture | β | Logic Array Blocks with FastTrack interconnect |