Altera

EPF8820ATC144-11 - FLEX 8000 FPGA 8K Gates 144-TQFP | Altera

Name: EPF8820ATC144-11 - FLEX 8000 FPGA 8K Gates 144-TQFP | Altera
Brand: Altera
SKU: EPF8820ATC144-11
Price: 23.1 USD
Availability: InStock

MPN: EPF8820ATC144-11 ✗ End of Life

In Stock Ships in 1-3 business days

5.0 V nominal Vdss 144-pin TQFP (Plastic Thin Quad Flat Pack) Package up to 125 MHz Speed

From $23.1 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$35	$35.00
10	$32.5	$325.00
100	$29.75	$2,975.00
500	$26.4	$13,200.00
1,000	$23.1	$23,100.00

ℹ️ All prices are in USD

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EPF8820ATC144-11 Overview

The Intel (formerly Altera) EPF8820ATC144-11 is a member of the FLEX 8000 family of CMOS SRAM-based Field Programmable Gate Arrays, integrating 8,000 usable gates and 672 logic cells in a 144-pin TQFP (Plastic Thin Quad Flat Pack) package. Speed grade -11 indicates a specific propagation-delay bin, with the wider FLEX 8000 family operating up to 125 MHz internally and supporting 112 user I/O in this TQFP-144 form factor. Supply voltage is 5.0 V nominal with MultiVolt I/O capability (3.3 V or 5.0 V tolerance).

A Field Programmable Gate Array (FPGA) is a programmable logic device (PLD) whose logic and interconnections are configured by CMOS SRAM cells, distinguishing it from CPLDs (which use non-volatile fuses or flash) and ASICs (custom-masked). Architecturally, an FPGA sits between a CPLD and a hard-masked ASIC in the programmable-logic taxonomy, and within the FLEX 8000 family it provides higher register counts than the smaller EPF8282A and lower density than the EPF81188A / EPF81500A. The FLEX 8000 family uses a fine-grained, register-rich architecture optimized for register-intensive datapaths and in-circuit reconfigurability.

Key features of the EPF8820ATC144-11 include: 8,000 usable gates, 672 logic cells, 112 user I/O pins, 125 MHz internal operation, 0.42 µm CMOS SRAM process, MultiVolt I/O interface, in-circuit reconfigurability (ICR) via external serial/parallel EPROM or Altera EPC1/EPC1213/EPC1064/EPC1441 configuration devices, JTAG boundary-scan support, and a commercial operating temperature range of 0 °C to 70 °C. The 144-pin TQFP package measures 20 mm × 20 mm with 0.5 mm pitch.

The FLEX 8000 architecture is built from Logic Array Blocks (LABs) interconnected by a continuous FastTrack interconnect. Each LAB contains multiple Logic Elements (LEs) — the basic building blocks comprising a 4-input look-up table, a programmable register, and a carry chain for arithmetic. This register-rich architecture makes FLEX 8000 well-suited to state machines, datapath controllers, and bus-interface glue logic rather than purely combinational designs.

Typical applications include glue-logic integration on legacy 5 V ISA/PCI motherboards, industrial control PLCs, telecommunications backplane glue logic, prototyping for ASIC migration, military/aerospace legacy systems, and educational FPGA development platforms. The MultiVolt I/O allows direct interfacing with both 3.3 V and 5.0 V devices without level shifters.

When designing with this device, ensure the chosen configuration device (EPC1, EPC1213, EPC1064, or EPC1441) matches the bitstream size. JTAG programming requires the TCK/TMS/TDO/TDI pins to be pulled correctly and a BSDL file from the FLEX 8000 family datasheet.

This page synthesizes distributor stock, drop-in Altera/Intel alternatives, and configuration-design guidance beyond the bare datasheet — covering compatibility with the FLEX 8000 family lineup and modern supply-chain alternatives.

Drop-in alternatives for EPF8820ATC144-11 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF8820ATC144-11 (same form factor and footprint) — differing in Package, Process Technology, Configuration Method, Speed Grade, Operating Temperature.

EPF8820ATC100-2

Altera

Package: TQFP-100, 100-pin Thin Quad Flat Pack

Process Technology: SRAM-based, volatile (requires external configuration memory)

Configuration Method: Passive Serial / Passive Parallel / Active Serial / JTAG