EPM240T100I5N vs EPM240T100A5N Comparison
Detailed side-by-side comparison of EPM240T100I5N by Intel and EPM240T100A5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N β ActiveSpecification Comparison
| Parameter | EPM240T100I5N | EPM240T100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.45 | $7.05 |
| Series | MAX II | β |
| Family | MAX II CPLDs | MAX II |
| Logic Elements (LE) | 240 | 240 |
| Equivalent Macrocells | 192 | β |
| User I/O | 80 | β |
| User Flash Memory (UFM) | 8 Kbits | β |
| Package | 100-pin TQFP (T100) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Process Technology | 0.18 Β΅m, 6-layer-metal flash | 0.18 Β΅m |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O Banks (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | β |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial) | 0C to +85C (commercial, "A5N" suffix) |
| Propagation Delay (typ.) | [DATA_NEEDED: tPD value] | β |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant | Compliant (Pb-free) |
| Macro Cells | β | 192 |
| User I/O Count | β | 80 |
| Pin-to-Pin Logic Delay (tPD) | β | 4.7 ns |
| Maximum Internal Frequency | β | 201.1 MHz |
| Supply Voltage | β | 2.5 V / 3.3 V |
| I/O Bank Count | β | 4 (multi-voltage) |
| Configuration Memory | β | On-chip Flash (instant-on) |