EPM240T100I5N - 240 LE MAX II CPLD, 100-pin TQFP | Intel
MPN: EPM240T100I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.5 | $11.50 |
| 10 | $10.35 | $103.50 |
| 100 | $9.2 | $920.00 |
| 500 | $8.3 | $4,150.00 |
| 1,000 | $7.45 | $7,450.00 |
EPM240T100I5N Overview
What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-configurable digital logic IC that replaces discrete glue-logic gates, muxes, and small state machines. CPLDs sit below FPGAs in the programmable-logic taxonomy (CPLD -> programmable logic -> digital IC -> semiconductor), offering deterministic timing, single-chip boot, and lower static power than equivalent FPGA implementations. The MAX II architecture moves the configuration storage into flash so the device behaves like an ASIC at power-up with no external PROM required.
Key features of the EPM240T100I5N include 80 user I/O pins, four I/O banks with independent VCCIO rails, a JTAG-based IEEE 1149.1 boundary-scan / ISP interface, and a MultiVolt core that operates from a single 3.3 V supply while interfacing to mixed-voltage rails. The device achieves typical pin-to-pin propagation delays around 7 ns and supports in-system programmability through the Quartus II toolchain.
From an architecture standpoint, the 240 LEs are organized into Logic Array Blocks (LABs), each containing 10 LEs, with interconnect driven by the MultiTrack interconnect fabric. The embedded UFM (8 Kbits) can store user data such as serial numbers, calibration constants, or boot parameters, eliminating a small EEPROM in many designs.
Typical applications include I/O expansion and bus bridging between microcontrollers and peripherals, power-sequencer and supervisory logic, glue-logic replacement on industrial PCBs, LED-control drivers, and protocol-bridging glue for I2C/SPI/UART multiplexing. Its flash-backed instant-on behavior is also valued in motor-control and safety-critical industrial systems.
Designers should note that the MAX II family is in mature, long-life supply status; verify long-term availability with the vendor before committing to new high-volume designs, and consider the MAX V family (5M240ZT100C5N) as a pin-compatible next-generation option with 1.8 V core.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes beyond the manufacturer datasheet, organized for engineers sourcing the EPM240T100I5N today.
Drop-in alternatives for EPM240T100I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM240T100I5N (same form factor and footprint) — differing in Package, Operating Temperature, RoHS Status, Process Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM240T100I5
✅ Drop-In✓ In Stock
$5.88 / Unit
View Datasheet →EPM240T100C5N
✅ Drop-In✓ In Stock
$4.32 / Unit
View Datasheet →EPM240T100C4N
✅ Drop-In✓ In Stock
$6.1 / Unit
View Datasheet →EPM240T100C3N
✅ Drop-In✓ In Stock
$9.05 / Unit
View Datasheet →EPM240M100I5N
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPM240T100I5N Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Family | MAX II CPLDs |
| Logic Elements (LE) | 240 |
| Equivalent Macrocells | 192 |
| User I/O | 80 |
| User Flash Memory (UFM) | 8 Kbits |
| Package | 100-pin TQFP (T100) |
| Process Technology | 0.18 µm, 6-layer-metal flash |
| Supply Voltage - Core (VCCINT) | 3.3 V |
| Supply Voltage - I/O Banks (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Operating Temperature | -40 °C to +100 °C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
EPM240T100I5N Pin Configuration
| Pin 1 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 2 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 3 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 4 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 5 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 6 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 7 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 8 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 9 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 10 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 11 | VCCIO1 — I/O bank 1 supply (1.5/1.8/2.5/3.3 V) |
| Pin 12 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 13 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 14 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 15 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 16 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 17 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 18 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 19 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 20 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 21 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 22 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Pin 23 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 24 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 25 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 26 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 27 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 28 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 29 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 30 | I/O — User I/O (bank 2, MultiVolt) |
| Pin 31 | TDI — JTAG Test Data In |
| Pin 32 | TMS — JTAG Test Mode Select |
| Pin 33 | TCK — JTAG Test Clock |
| Pin 34 | GND — Ground |
| Pin 35 | VCCINT — Core supply (3.3 V) |
| Pin 36 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 37 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 38 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 39 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 40 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 41 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 42 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 43 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 44 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 45 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 46 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Pin 47 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 48 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 49 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 50 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 51 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 52 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 53 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 54 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 55 | I/O — User I/O (bank 3, MultiVolt) |
| Pin 56 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Pin 57 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 58 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 59 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 60 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 61 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 62 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 63 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 64 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 65 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 66 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 67 | VCCIO4 — I/O bank 4 supply (1.5/1.8/2.5/3.3 V) |
| Pin 68 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 69 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 70 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 71 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 72 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 73 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 74 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 75 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 76 | I/O — User I/O (bank 4, MultiVolt) |
| Pin 77 | TDO — JTAG Test Data Out |
| Pin 78 | GND — Ground |
| Pin 79 | VCCINT — Core supply (3.3 V) |
| Pin 80 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 81 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 82 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 83 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 84 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 85 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 86 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 87 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 88 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 89 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 90 | VCCIO1 — I/O bank 1 supply (1.5/1.8/2.5/3.3 V) |
| Pin 91 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 92 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 93 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 94 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 95 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 96 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 97 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 98 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 99 | I/O — User I/O (bank 1, MultiVolt) |
| Pin 100 | GND — Ground |
Typical Applications
EPM240T100I5N is suitable for 7 applications: Microcontroller I/O Expansion & Bus Bridging, Industrial Control & Factory Automation Logic, Power Sequencing & Supervisory Logic, LED Display & Lighting Control, Automotive & Transportation Subsystems (non-safety), Test & Measurement Front-End Logic, Legacy System Modernization & 74-Series Replacement.
Microcontroller I/O Expansion & Bus Bridging
The EPM240T100I5N adds configurable GPIO and protocol bridges to MCUs that have too few pins or lack a needed interface (I2C-to-SPI, UART-to-parallel, etc.). With 240 LEs, 80 user I/Os, and 8 Kbits of UFM, the device can implement state machines, timing generators, and small FIFOs in a single non-volatile chip. Its MultiVolt I/O supports direct interfacing to 1.5 V / 1.8 V / 2.5 V / 3.3 V MCU rails without level shifters. The industrial -40 °C to +100 °C range makes the part suitable for outdoor or factory-floor designs.
Recommended
Industrial Control & Factory Automation Logic
In PLCs, motor controllers, and sensor-conditioning front-ends, the EPM240T100I5N serves as deterministic glue logic that boots in microseconds and is immune to soft-config errors because of its on-chip flash storage. Its 80 user I/O and four MultiVolt banks handle mixed 5 V / 3.3 V / 1.8 V sensor rails, while the 240-LE capacity covers encoder decoding, PWM shaping, and fault-handling state machines. The industrial temperature range matches IEC 60068 harsh-environment profiles and is supported by a long-life-cycle product program from Intel.
Recommended
Power Sequencing & Supervisory Logic
The EPM240T100I5N can replace discrete supervisor ICs by sequencing multiple power rails using configurable delays and monitoring inputs from PG (power-good) signals. Its 8 Kbits of UFM allow storage of rail-trip thresholds and fault logs without an external EEPROM. MultiVolt I/O lets one CPLD supervise 1.0 V, 1.8 V, 3.3 V, and 5 V rails concurrently, and the deterministic 7 ns-class tPD keeps timing margins tight for hot-swap and brown-out events.
Recommended
LED Display & Lighting Control
LED walls, architectural lighting, and signage benefit from the EPM240T100I5N's ability to drive 80 outputs with precise PWM timing, color-mixing math, and DMX-512 / SPI / I2C input parsing. The 8 Kbits UFM hold calibration data for pixel-level brightness compensation. Because the device boots instantly from flash, displays come up with their last pattern even after a power cycle, no re-flash needed.
Recommended
Automotive & Transportation Subsystems (non-safety)
Although not AEC-Q100 qualified, the EPM240T100I5N's industrial temperature range and flash-backed non-volatility make it suitable for non-safety automotive subsystems such as body-control accessories, infotainment interface bridges, and aftermarket modules. Its small TQFP-100 footprint and Quartus II toolchain shorten design cycles for short-run vehicle programs. Designers targeting safety-critical rails should still pick an AEC-Q100 part.
Recommended
Test & Measurement Front-End Logic
In bench-top instruments, the EPM240T100I5N handles trigger routing, channel multiplexing, range switching, and counter prescalers that would otherwise require multiple 74-series packages. The MultiVolt I/O connects directly to 1.8 V ADCs, 3.3 V FPGAs, and 5 V analog front-ends. The 8 Kbits UFM stores per-unit calibration constants readable over JTAG, reducing manual trimming in production.
Recommended
Legacy System Modernization & 74-Series Replacement
The EPM240T100I5N consolidates dozens of 74HC/74AHC logic gates, muxes, and flip-flops into one programmable device, simplifying PCB layout, BOM, and inventory. Engineers redesigning legacy boards can re-implement standard logic functions in Quartus II HDL or schematic capture and migrate the schematic netlist without changing the TQFP-100 footprint. Re-programmability also enables late-stage ECOs that would otherwise require a board spin.
Recommended
Recommended Products Summary
Engineering reference data for EPM240T100I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240T100I5 | EPM240T100C5N | EPM240T100C4N | EPM240T100C3N | EPM240M100I5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 (T100) | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (M100) - same footprint |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Series | MAX II | MAX II | MAX II | MAX II | MAX II | MAX II |
| Logic Elements | 240 | 240 | 240 | 240 | 240 | 240 |
| User I/O | 80 | 80 | 80 | 80 | 80 | 80 |
| Temperature Grade | Industrial (-40 to +100 °C) | Industrial | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Industrial |
| Speed Grade | I5 (fastest industrial) | I5 | C5 | C4 | C3 | I5 |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
Key Differentiators
- Industrial temperature grade (-40 to +100 °C) for harsh environments (vs EPM240T100C5N)
- Fastest industrial speed grade available in TQFP-100 footprint (vs EPM240T100C4N)
- Non-volatile flash configuration - true instant-on with no boot PROM (vs SRAM-based small FPGAs)
- On-chip 8 Kbit UFM eliminates external EEPROM in many designs (vs Discrete CPLD + external EEPROM)
Design Notes
The EPM240T100I5N requires a clean 3.3 V VCCINT rail and up to four VCCIO rails (1.5/1.8/2.5/3.3 V) for its I/O banks. Decouple each VCCIO pin with a 0.1 µF X7R ceramic placed within 3 mm of the package, and add a single 10 µF bulk capacitor per bank on the same side of the PCB. Estimated: typical ICCINT is in the low milliampere range during operation; peak inrush during in-system programming (ISP) may reach tens of milliamperes, so size the 3.3 V regulator to handle ISP transients.
TQFP-100 has 0.5 mm pitch leads - use a 4-layer PCB with continuous ground plane under the device to provide a low-impedance return path for switching outputs. Route JTAG signals (TCK, TMS, TDI, TDO) away from clock or high-speed I/O traces to avoid noise coupling into the boundary-scan logic. Keep all four VCCIO planes as islands tied only at the decoupling caps to prevent cross-bank noise injection.
Do not leave unused I/O pins floating - configure them as outputs driving a defined logic level, or as inputs with weak pull-ups enabled in the Quartus II pin assignment. Floating inputs can draw excess ICCIO current and may cause inadvertent toggling. Also, verify VCCIO bank assignments before power-up; driving a 5 V signal into a 3.3 V VCCIO bank will damage the I/O. Refer to the MAX II handbook for the exact bank-to-pin mapping for the TQFP-100 package.
For JTAG-ISP chains that include the EPM240T100I5N alongside other devices, place a 4.7 kΩ pull-up on TCK and TMS, and TMS-to-ground if ISP is unused, to keep the JTAG state machine in a known reset state during power-up. Estimated: trace lengths of TCK/TMS/TDI/TDO should not exceed 150 mm on FR-4 without a series-termination resistor to avoid ringing on the 10-30 MHz TCK edge used by the ByteBlaster or USB-Blaster download cables.
Compliance Information
RoHS and lead-free per Intel/Altera product declaration and DigiKey/Mouser listings. Not AEC-Q100 qualified - the I-grade temperature range is industrial, not automotive qualified. Verify JEDEC J-STD-020 MSL rating from the device label before reflow.
