EPM3128AFC256-7N vs EPM3128ATC100-10NS Comparison
Detailed side-by-side comparison of EPM3128AFC256-7N by Altera and EPM3128ATC100-10NS by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128AFC256-7N
EPM3128AFC256-7N - 128-Macro 7.5ns MAX 3000A CPLD | Altera
EPM3128AFC256-7N NrndIntel
EPM3128ATC100-10NS
EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel
EPM3128ATC100-10NS ObsoleteSpecification Comparison
| Parameter | EPM3128AFC256-7N | EPM3128ATC100-10NS |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.85 | $6.50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based MAX | β |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | β |
| User I/Os | 98 | 80 |
| Propagation Delay (tPD) | 7.5 ns | β |
| Internal fMAX | 192.3 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | 3.3 V |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic Family | CMOS | β |
| Programmability | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) | In-system (ISP), IEEE Std. 1532 |
| Package | 256-BGA (FineLine, FBGA) | TQFP-100 |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| Pin Count | β | 100 |
| Pin-to-Pin Logic Delay (tPD) | β | 10 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| Logic-Level Compatibility | β | 5.0 V, 3.3 V, 2.5 V |
| Boundary Scan | β | IEEE 1149.1 JTAG |
| Configuration Memory | β | EEPROM (non-volatile) |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |