Intel

EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel

MPN: EPM3128ATC100-10NS ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss TQFP-100 Package up to 227.3 MHz Speed EEPROM (non-volatile) Memory

From $6.5 USD / Unit

MOQ: 1 |

Price updated: 2026-09-12

Volume Pricing

Qty	Unit Price	Extended
1	$10.13	$10.13
10	$9.2	$92.00
100	$8.1	$810.00
500	$7.3	$3,650.00
1,000	$6.5	$6,500.00

ℹ️ All prices are in USD

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EPM3128ATC100-10NS Overview

The Intel EPM3128ATC100-10NS is a member of the MAX 3000A family of Complex Programmable Logic Devices (CPLDs), offering 128 macro cells and 80 user I/O pins in a 100-pin Thin Quad Flat Pack (TQFP) package with 10 ns pin-to-pin logic delay. It operates from a 3.3 V core supply and supports MultiVolt I/O, which allows its I/O banks to interface with 5.0 V, 3.3 V, or 2.5 V logic levels by powering VCCIO at the appropriate rail. The device provides in-system programmability (ISP) compliant with IEEE Std. 1532, enabling concurrent programming across multiple PLD vendors.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macro-cell arrays with a programmable interconnect matrix. It sits between simple logic gates and FPGAs in the programmable logic hierarchy and is widely used for glue logic, bus interfacing, state-machine control, and power-up sequencing in digital systems. The MAX 3000A family belongs to Intel's (formerly Altera's) classic CPLD portfolio, providing instant-on, deterministic timing, and high pin-to-pin speed that FPGAs cannot match for small, fast, fixed-function blocks.

Key features of the EPM3128ATC100-10NS include 4.5 ns pin-to-pin logic delays with counter frequencies up to 227.3 MHz, programmable interconnect that allows any pin to drive any macro cell or I/O, and JTAG-based boundary-scan testing per IEEE 1149.1. The 80 available I/O pins (out of 100 total package pins) share 4 dedicated input clocks and a global clear network, while 3.3 V core operation keeps power dissipation low for industrial and consumer applications.

Architecturally, the device uses EEPROM-based configuration cells, providing non-volatile storage that retains the logic design without external memory. The MAX 3000A macro cells implement sum-of-products logic with configurable flip-flops and a wide fan-in AND-OR structure, while the interconnect matrix (the so-called "Programmable Interconnect Array" or PIA) routes signals between logic array blocks with predictable timing.

Typical applications include bus-interface bridging, address decoding and chip-select generation, state-machine and sequencer implementation, power-up and reset sequencing, peripheral I/O expansion, and glue-logic replacement of discrete 74-series TTL. Its 5 V-tolerant I/O and fast propagation delay also suit industrial control and motor-drive front ends.

When designing with this device, ensure VCCINT is a regulated 3.3 V and VCCIO is set according to the I/O logic level. Decoupling must include 0.1 uF and 1 uF capacitors placed within 5 mm of each supply pin. JTAG chain order should be planned before PCB layout to avoid re-spinning the board for testability.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. The EPM3128ATC100-10NS is the extended-temperature (N suffix) variant of the EPM3128ATC100-10.

Drop-in alternatives for EPM3128ATC100-10NS — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPM3128ATC100-10NS (same form factor and footprint) — differing in Package, Operating Temperature, In-System Programmability, Propagation Delay (tPD), Usable Gates.

EPM3128AFC256-7N

Altera

Package: 256-BGA (FineLine, FBGA)

Operating Temperature: 0 C to +70 C (commercial)

Propagation Delay (tPD): 7.5 ns