EPM3128AFI256-10N vs EPM3256AFC256-7 Comparison

Detailed side-by-side comparison of EPM3128AFI256-10N by Altera and EPM3256AFC256-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128AFI256-10N EPM3256AFC256-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $12.10
Family MAX 3000A MAX 3000A
Logic Density 2.5K gates β€”
Macro Cells 128 256
User I/Os 98 161
Speed Grade -10 (10 ns pin-to-pin) -7
Propagation Delay (tPD) 10 ns β€”
Counter Frequency (max) 227.3 MHz β€”
Logic Family CMOS, EEPROM-based β€”
Supply Voltage (Core) 3.3 V β€”
I/O Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt) 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
In-System Programmability Yes (JTAG / IEEE 1149.1) IEEE Std. 1532-compliant 3.3-V ISP
Package 256-ball FineLine BGA (FBGA-256) FBGA-256 (FineLine BGA), 256 balls
Operating Temperature -40C to +85C (industrial, per 'I' suffix) 0 Β°C to 70 Β°C (Commercial)
Pin Count 256 β€”
RoHS Status Compliant [DATA_NEEDED: RoHS compliance status]
Configuration Memory EEPROM (non-volatile) β€”
PCI Compliance PCI Local Bus Spec Rev 2.2 β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 16
Usable Gates β€” 10,000
Pin-to-Pin Logic Delay β€” 4.5 ns (max)
Counter Frequency β€” 227.3 MHz (max)
Propagation Delay (tpd) β€” 10 ns
Core Voltage β€” 3.3 V
Process Technology β€” CMOS EEPROM, 0.30 Β΅m
Boundary-Scan Test β€” JTAG (IEEE 1149.1)

Datasheets & Resources

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