EPM3128ATC100-5N vs EPM3128ATC100-10NS Comparison
Detailed side-by-side comparison of EPM3128ATC100-5N by Intel and EPM3128ATC100-10NS by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3128ATC100-5N
EPM3128ATC100-5N - MAX 3000A CPLD, 128 Macrocells, 80 I/O | Intel
EPM3128ATC100-5N β ActiveIntel
EPM3128ATC100-10NS
EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel
EPM3128ATC100-10NS ObsoleteSpecification Comparison
| Parameter | EPM3128ATC100-5N | EPM3128ATC100-10NS |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $6.50 |
| Device Family | MAX 3000A | β |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | β |
| Usable Gates | Up to 10,000 | β |
| User I/Os | 80 | 80 |
| Propagation Delay (tPD) | 5 ns | β |
| Maximum Internal Frequency | 192.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| Programming Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes (IEEE Std. 1532) | β |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | β |
| Package | TQFP-100 (TC100) | TQFP-100 |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Family | β | MAX 3000A |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 128 |
| Pin Count | β | 100 |
| Pin-to-Pin Logic Delay (tPD) | β | 10 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | β | 3.3 V |
| Supply Voltage - I/O (VCCIO) | β | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | β | 5.0 V, 3.3 V, 2.5 V |
| Programmability | β | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | β | IEEE 1149.1 JTAG |
| Configuration Memory | β | EEPROM (non-volatile) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |