EPM3128ATC100-7N vs EPM3128ATI100-10 Comparison
Detailed side-by-side comparison of EPM3128ATC100-7N by Intel and EPM3128ATI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3128ATC100-7N - MAX 3000A 128-Macrocell CPLD, 7.5 ns, TQFP-100 | Intel (Altera)
EPM3128ATC100-7N NrndAltera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 β ActiveSpecification Comparison
| Parameter | EPM3128ATC100-7N | EPM3128ATI100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.52 | $8.40 |
| Family | MAX 3000A | MAX 3000A |
| Macro Cells | 128 | 128 |
| Usable Gates | Up to 10,000 | 2,500 |
| Number of I/Os | 80 | β |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Counter Frequency (max) | 227.3 MHz | β |
| Supply Voltage - Core | 3.3 V | β |
| I/O Interface Levels | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | β |
| In-System Programmability | Yes (IEEE 1532 / JTAG) | β |
| Program Memory Type | EEPROM (non-volatile) | β |
| Operating Temperature | 0C to +70C (Commercial) | -40 Β°C to +85 Β°C (industrial) |
| Package | TQFP-100 (100-pin TQFP, fine-line BGA-256 noted in third-party listings) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Family | CMOS | β |
| Speed Grade | -7 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| User I/Os | β | 80 |
| Logic Elements / LABs | β | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| MultiVolt I/O Levels | β | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | β | EEPROM, 3.3 V in-system (JTAG) |
| Process Technology | β | CMOS EEPROM |
| Open-Drain Output Option | β | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | β | IEEE 1149.1 compliant |