EPM3256AFC256-10 vs EPM3256AFC256-7 Comparison

Detailed side-by-side comparison of EPM3256AFC256-10 by Altera and EPM3256AFC256-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-10 EPM3256AFC256-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $19.95 $12.10
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 256
Usable Gates 5,000 10,000
Logic Array Blocks (LABs) 16 (16 macrocells each) 16
Maximum User I/Os 161 β€”
Propagation Delay (tPD) 10 ns β€”
Internal Counter Frequency (fCNT) 95.2 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Voltage Tolerance 5.0 V tolerant β€”
In-System Programmability Yes (3.3 V ISP via JTAG IEEE 1149.1) IEEE Std. 1532-compliant 3.3-V ISP
Operating Temperature 0Β°C to +70Β°C (Commercial) 0 Β°C to 70 Β°C (Commercial)
Package 256-ball FBGA (Fine-Line BGA) FBGA-256 (FineLine BGA), 256 balls
Pitch [DATA_NEEDED: BGA ball pitch] β€”
Mounting Type Surface Mount β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
User I/Os β€” 161
Pin-to-Pin Logic Delay β€” 4.5 ns (max)
Counter Frequency β€” 227.3 MHz (max)
Propagation Delay (tpd) β€” 10 ns
Core Voltage β€” 3.3 V
I/O Compatibility β€” 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
Process Technology β€” CMOS EEPROM, 0.30 Β΅m
Boundary-Scan Test β€” JTAG (IEEE 1149.1)
Speed Grade β€” -7

Datasheets & Resources

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