EPM3256AFC256-7 vs EPM3256AFC256-10 Comparison
Detailed side-by-side comparison of EPM3256AFC256-7 by Altera and EPM3256AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 β Last Time BuySpecification Comparison
| Parameter | EPM3256AFC256-7 | EPM3256AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.10 | $19.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 (16 macrocells each) |
| Usable Gates | 10,000 | 5,000 |
| User I/Os | 161 | β |
| Pin-to-Pin Logic Delay | 4.5 ns (max) | β |
| Counter Frequency | 227.3 MHz (max) | β |
| Propagation Delay (tpd) | 10 ns | β |
| Core Voltage | 3.3 V | β |
| I/O Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | β |
| Process Technology | CMOS EEPROM, 0.30 Β΅m | β |
| In-System Programmability | IEEE Std. 1532-compliant 3.3-V ISP | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | β |
| Package | FBGA-256 (FineLine BGA), 256 balls | 256-ball FBGA (Fine-Line BGA) |
| Operating Temperature | 0 Β°C to 70 Β°C (Commercial) | 0Β°C to +70Β°C (Commercial) |
| Speed Grade | -7 | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | β | CMOS (EEPROM-based) |
| Maximum User I/Os | β | 161 |
| Propagation Delay (tPD) | β | 10 ns |
| Internal Counter Frequency (fCNT) | β | 95.2 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Voltage Tolerance | β | 5.0 V tolerant |
| Pitch | β | [DATA_NEEDED: BGA ball pitch] |
| Mounting Type | β | Surface Mount |