EPM3256AFC256-7 vs EPM3256ATC144-7 Comparison

Detailed side-by-side comparison of EPM3256AFC256-7 by Altera and EPM3256ATC144-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-7 EPM3256ATC144-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $12.10 $17.06
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macro Cells 256 β€”
Logic Array Blocks (LABs) 16 β€”
Usable Gates 10,000 β€”
User I/Os 161 116
Pin-to-Pin Logic Delay 4.5 ns (max) β€”
Counter Frequency 227.3 MHz (max) β€”
Propagation Delay (tpd) 10 ns β€”
Core Voltage 3.3 V β€”
I/O Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) β€”
Process Technology CMOS EEPROM, 0.30 Β΅m β€”
In-System Programmability IEEE Std. 1532-compliant 3.3-V ISP β€”
Boundary-Scan Test JTAG (IEEE 1149.1) β€”
Package FBGA-256 (FineLine BGA), 256 balls TQFP-144 (LFQFP, gull-wing)
Operating Temperature 0 Β°C to 70 Β°C (Commercial) 0C to +70C (Commercial)
Speed Grade -7 -7
RoHS Status [DATA_NEEDED: RoHS compliance status] β€”
Macrocells β€” 256
Logic Elements / Gates β€” 600 to 10,000 usable gates
Propagation Delay (tPD) β€” 7.5 ns
Counter Frequency (fCNT) β€” 227.3 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
Supply Voltage - I/O (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V
In-System Programming β€” IEEE Std. 1532 compliant, 3.3 V ISP
Pin Count β€” 144
Mounting Type β€” Surface Mount
PCI Compliance β€” PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10)
JTAG Support β€” IEEE Std. 1149.1 boundary-scan

Datasheets & Resources

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