EPM3256AFC256-7 vs EPM3512AFC256-7 Comparison

Detailed side-by-side comparison of EPM3256AFC256-7 by Altera and EPM3512AFC256-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-7 EPM3512AFC256-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $12.10 $58.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 β€”
Logic Array Blocks (LABs) 16 16
Usable Gates 10,000 10,000
User I/Os 161 β€”
Pin-to-Pin Logic Delay 4.5 ns (max) 7.5 ns
Counter Frequency 227.3 MHz (max) β€”
Propagation Delay (tpd) 10 ns β€”
Core Voltage 3.3 V β€”
I/O Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) β€”
Process Technology CMOS EEPROM, 0.30 Β΅m β€”
In-System Programmability IEEE Std. 1532-compliant 3.3-V ISP β€”
Boundary-Scan Test JTAG (IEEE 1149.1) β€”
Package FBGA-256 (FineLine BGA), 256 balls 256-ball FineLine BGA (FBGA-256)
Operating Temperature 0 Β°C to 70 Β°C (Commercial) [DATA_NEEDED: operating temperature grade]
Speed Grade -7 β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Macrocells β€” 512
User I/O Pins β€” 212
Counter Frequency (max) β€” 227.3 MHz
Supply Voltage - Core (VCCINT) β€” 3.0 V to 3.6 V (3.3 V typ.)
I/O Voltage (VCCIO) β€” 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming β€” EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant)
Mounting Type β€” Surface Mount
Configuration Memory β€” Non-volatile EEPROM

Datasheets & Resources

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