EPM3512AFC256-7N vs EPM3512AFC256-3N Comparison
Detailed side-by-side comparison of EPM3512AFC256-7N by Altera and EPM3512AFC256-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoleteSpecification Comparison
| Parameter | EPM3512AFC256-7N | EPM3512AFC256-3N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $61.00 | $23.40 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 208 | β |
| Logic Blocks | 16 (32 macrocells each) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| 5V Tolerant I/O | Yes | β |
| In-System Programmability | IEEE Std. 1532 compliant | β |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP |
| Process Technology | CMOS EEPROM, 0.30 um | β |
| Package | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FC-256) |
| Operating Temperature | 0 C to 70 C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum Operating Frequency | β | 116.3 MHz |
| Pin-to-Pin Delay (tPD) | β | 3.5 ns (speed grade -3) |
| Speed Grade | β | -3 (slowest in family) |
| Configuration Memory | β | Non-volatile EEPROM |