EPM3512AQC20810 vs EPM3128ATC100-10N Comparison

Detailed side-by-side comparison of EPM3512AQC20810 by Altera and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC20810 EPM3128ATC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $16.80 $5.20
Family MAX 3000A MAX 3000A
Logic Type CPLD (EEPROM-based, non-volatile) β€”
Macro Cells 512 128
User I/Os 172 β€”
Logic Array Blocks (LABs) 16 β€”
Usable Gates (equivalent) 10000 β€”
Package 208-pin PQFP (PQ208) 100-pin TQFP (14 x 14 x 1.0 mm)
Speed Grade -10 (tPD = 10 ns) β€”
Propagation Delay (tPD) 10 ns 10 ns
Maximum Internal Frequency 132 MHz β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V β€”
In-System Programmability Yes (IEEE 1149.1 JTAG, 3.3 V ISP) β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 compliant β€”
Operating Temperature (commercial) 0 Β°C to +70 Β°C β€”
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Configuration Memory On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention CMOS EEPROM (non-volatile, instant-on)
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Product Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 2500
Number of I/O β€” 80
Logic Elements / Blocks β€” 8 LABs (16 macrocells each)
Maximum Internal Frequency (fMAX) β€” 98 MHz
Supply Voltage VCCINT β€” 3.3 V
I/O Bank Voltage VCCIO β€” 3.3 V or 2.5 V (selectable)
In-System Programming β€” IEEE Std. 1532-compliant ISP via JTAG
Operating Temperature β€” 0 Β°C to +70 Β°C (commercial)
Mounting Type β€” Surface Mount
Lead-Free β€” Yes
MSL Level β€” 3 (per JEDEC J-STD-020)

Datasheets & Resources

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