EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
MPN: EPM3128ATC100-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $10.13 | $10.13 |
| 10 | $9.12 | $91.20 |
| 100 | $7.85 | $785.00 |
| 500 | $6.9 | $3,450.00 |
| 1,000 | $5.95 | $5,950.00 |
| 3,000 | $5.2 | $15,600.00 |
EPM3128ATC100-10N Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays with a central programmable interconnect matrix. CPLDs sit in the hierarchy between simple SPLDs (PALs/GALs) and larger FPGAs, offering deterministic, single-clock-cycle propagation delays and instant-on non-volatile configuration. The MAX 3000A family uses CMOS EEPROM configuration memory, IEEE Std. 1532-compliant in-system programmability (ISP), and belongs to the broader power-management and logic-IC semiconductor category.
Key features include 128 macrocells (2500 usable gates), 80 user I/O pins, an internal fMAX of 98 MHz (per the FPGAkey datasheet summary), 3.3 V VCCINT operation, and selectable 3.3 V or 2.5 V VCCIO banks for mixed-voltage I/O. The device is pin-compatible with other MAX 3000A 100-pin TQFP variants and supports JTAG-based boundary-scan testing alongside ISP. The non-volatile EEPROM cells eliminate the need for an external boot PROM and the part powers up instantly in a user-defined state.
Architecturally, the EPM3128ATC100-10N organizes its 128 macrocells into 8 Logic Array Blocks (LABs) of 16 macrocells each, connected through a Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array feeding a configurable flip-flop with product-term clock, clear, and preset controls, supporting combinatorial, registered, and buried logic without consuming I/O.
Typical applications include I/O expansion and bus bridging on legacy glue-logic boards, address decoding and interrupt steering on industrial controllers, state-machine replacement in white-goods motor control, and pin-compatible MAX 3000A migration paths. Designers in factory automation, telecom line cards, and embedded computing rely on this part for deterministic timing and field-reprogrammability.
Designers should pay attention to VCCIO bank configuration: 3.3 V allows direct interface to 3.3 V logic, while 2.5 V setting enables 2.5 V system compatibility. The I/O pins share a common bus-friendly structure but each LAB region can source/sink up to 25 mA per pin with proper thermal management across the 100-pin TQFP (θJA around 35-40 °C/W depending on PCB copper). Avoid daisy-chaining JTAG; use a star topology for ISP chains longer than 4 devices.
This page synthesizes distributor pricing, IEEE Std. 1532 ISP-compatible drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet alone. Real-time stock and parametric comparison are derived from DigiKey, Mouser, Octopart, and LCSC as of 2026-09-12.
Drop-in alternatives for EPM3128ATC100-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM3128ATC100-10N (same form factor and footprint) — differing in Package, Operating Temperature, Configuration Memory, In-System Programmability, User I/Os.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM3128ATC100-10
✅ Drop-In✓ In Stock
$8.1 / Unit
View Datasheet →EPM3128ATC100-7N
✅ Drop-In✓ In Stock
$3.52 / Unit
View Datasheet →EPM3128ATC100-10N
✅ Drop-In✓ In Stock
$5.2 / Unit
View Datasheet →EPM3128AFC256-7N
✅ Drop-In✓ In Stock
$19.85 / Unit
View Datasheet →EPM3128ATC100-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2500 |
| Number of I/O | 80 |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | 10 ns |
| Maximum Internal Frequency (fMAX) | 98 MHz |
| Supply Voltage VCCINT | 3.3 V |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG |
| Package | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Operating Temperature | 0 °C to +70 °C (commercial) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| MSL Level | 3 (per JEDEC J-STD-020) |
EPM3128ATC100-10N Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 3 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 4 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 5 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 6 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 7 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 8 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 9 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 10 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 11 | VCCINT — Core 3.3 V supply |
| Pin 12 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 13 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 14 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 15 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 16 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 17 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 18 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 19 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 20 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 21 | GND — Ground reference |
| Pin 22 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 23 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 24 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 25 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 26 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 27 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 28 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 29 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 30 | I/O — Bidirectional user I/O pin (bank 2) |
| Pin 31 | GND — Ground reference |
| Pin 32 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 33 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 34 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 35 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 36 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 37 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 38 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 39 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 40 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 41 | VCCINT — Core 3.3 V supply |
| Pin 42 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 43 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 44 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 45 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 46 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 47 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 48 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 49 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 50 | I/O — Bidirectional user I/O pin (bank 3) |
| Pin 51 | GND — Ground reference |
| Pin 52 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 53 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 54 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 55 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 56 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 57 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 58 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 59 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 60 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 61 | GND — Ground reference |
| Pin 62 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 63 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 64 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 65 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 66 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 67 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 68 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 69 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 70 | I/O — Bidirectional user I/O pin (bank 4) |
| Pin 71 | GND — Ground reference |
| Pin 72 | TDI — JTAG Test Data In (ISP programming) |
| Pin 73 | TMS — JTAG Test Mode Select (ISP programming) |
| Pin 74 | TCK — JTAG Test Clock (ISP programming) |
| Pin 75 | NC — Not connected (per datasheet) |
| Pin 76 | VCCIO — I/O bank supply (3.3 V or 2.5 V) |
| Pin 77 | GCLK — Global clock input (dedicated) |
| Pin 78 | OE — Global Output Enable (dedicated input) |
| Pin 79 | NC — Not connected (per datasheet) |
| Pin 80 | VCCIO — I/O bank supply (3.3 V or 2.5 V) |
| Pin 81 | GND — Ground reference |
| Pin 82 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 83 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 84 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 85 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 86 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 87 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 88 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 89 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 90 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 91 | GND — Ground reference |
| Pin 92 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 93 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 94 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 95 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 96 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 97 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 98 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 99 | I/O — Bidirectional user I/O pin (bank 1) |
| Pin 100 | TDO — JTAG Test Data Out (ISP programming) |
Typical Applications
EPM3128ATC100-10N is suitable for 6 applications: Address Decoding & Bus Bridging on Legacy Glue Logic, Industrial Control State Machine Replacement, Telecom Line-Card I/O Expansion, Embedded Computing Glue Logic in Single-Board Computers, White-Goods Motor Control and Appliance Logic, Test & Measurement Equipment Front-End Logic.
Address Decoding & Bus Bridging on Legacy Glue Logic
The EPM3128ATC100-10N fits address decoding and bus-bridging roles because its 10 ns pin-to-pin propagation delay is deterministic and its 128 macrocells provide abundant product-term capacity for complex Chip-Select and interrupt-steering logic. Placed between a 3.3 V microcontroller and asynchronous peripheral buses, the device replaces 4-8 discrete PAL/GAL chips with a single in-system-reprogrammable CPLD, cutting PCB area by up to 60%. The IEEE Std. 1532 ISP interface lets field technicians update decode maps without desoldering the part, a key advantage over legacy bipolar PALs.
Recommended
Industrial Control State Machine Replacement
The EPM3128ATC100-10N is well-suited to replace discrete 74LS/74HC state machines in industrial controllers because its 98 MHz fMAX and 8 LABs support complex Moore/Mealy sequencers without microsequencer overhead. Its 80 user I/O pins map directly to typical PLC backplanes (32 inputs + 32 outputs + 16 control lines), and the non-volatile EEPROM means the controller boots into its last programmed state without an external boot PROM. The 3.3 V/2.5 V VCCIO flexibility lets the same board drive both 5 V-tolerant buffers (through level shifters) and native 2.5 V ASICs in mixed-voltage subsystems.
Recommended
Telecom Line-Card I/O Expansion
Telecom line cards use the EPM3128ATC100-10N as a low-cost I/O expander because its 80 I/O pins comfortably aggregate 16-32 E1/T1 channels, and the 10 ns tPD preserves timing margins for HDLC framing at 2.048 Mbps. The CPLD's deterministic 1-cycle latency simplifies hardware protocol validation, while ISP allows field upgrades when adding new channel bonding features. Its commercial 0-70 °C range suits temperature-controlled central-office shelves, and the TQFP-100 package is compatible with automated optical-inspection assembly lines used by contract manufacturers.
Recommended
Embedded Computing Glue Logic in Single-Board Computers
The EPM3128ATC100-10N integrates custom peripheral interfaces on Single-Board Computers (SBCs), where it bridges between ARM/SoC memory buses and legacy parallel ports, IDE interfaces, or custom FPGA mezzanine cards. Its 10 ns tPD adds less than one bus cycle of wait-state overhead at 100 MHz, and the 80 I/O pins handle simultaneous chip-select generation, interrupt aggregation, and GPIO expansion. The CPLD's 2500 usable gates give SBC designers headroom for last-minute feature additions without respinning the PCB.
Recommended
White-Goods Motor Control and Appliance Logic
The EPM3128ATC100-10N is widely deployed in washing machines, dishwashers, and HVAC control boards as the central sequencer for brushless DC motor commutation and safety interlocks. Its non-volatile EEPROM configuration boots the appliance into a known state even after multi-day power loss, and the 80 I/O pins drive triac-fired heater banks, relay coils, and Hall-effect sensor inputs concurrently. The TQFP-100 footprint survives wave-solder-compatible reflow profiles used by high-volume appliance contract manufacturers.
Recommended
Test & Measurement Equipment Front-End Logic
Test instruments use the EPM3128ATC100-10N to implement reconfigurable front-end routing matrices, trigger pattern generators, and scan-chain multiplexers. Its IEEE Std. 1532 ISP interface lets manufacturers ship instruments with field-upgradable trigger logic, extending product lifecycles without board rework. The 3.3 V/2.5 V VCCIO flexibility simplifies interfacing with modern ADCs and DACs while the 80 I/O count comfortably handles 32-channel multiplexer banks typical of mid-range oscilloscopes and data-acquisition systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-10 | EPM3128ATC100-7N | EPM3128AFC256-7N |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Macro Cells | 128 | 128 | 128 | 128 |
| User I/O | 80 | 80 | 80 | 80 |
| tPD (ns) | 10 ns | 10 ns | 7 ns (-30%) | 7 ns (-30%) |
| VCCINT | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| VCCIO Options | 3.3 V / 2.5 V | 3.3 V / 2.5 V | 3.3 V / 2.5 V | 3.3 V / 2.5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| ISP Standard | IEEE Std. 1532 | IEEE Std. 1532 | IEEE Std. 1532 | IEEE Std. 1532 |
| Lifecycle Status | NRND | NRND | NRND | NRND |
Key Differentiators
- Non-volatile EEPROM configuration enables instant-on operation (vs SRAM-based FPGAs (e.g., Cyclone series))
- Deterministic 10 ns pin-to-pin propagation delay (vs Microcontroller-based glue logic)
- IEEE Std. 1532-compliant ISP eliminates external programmer (vs Legacy bipolar PALs (e.g., PALCE16V8))
- Dual VCCIO bank flexibility (3.3 V / 2.5 V) (vs Single-supply CPLDs (e.g., MAX 7000S legacy))
Design Notes
Estimated: at VCCINT = 3.3 V and 80 I/O simultaneously switching at 5 MHz with 25 mA load per pin, the device core plus I/O current draw is approximately 80-120 mA. Use a 100 nF ceramic decoupling capacitor on every VCCINT pin and a 10 µF bulk capacitor near the package to suppress switching transients. Place decoupling capacitors within 3 mm of the supply pins to minimize inductance; vias to internal power planes must be at least 0.3 mm diameter for low ESL.
The 100-pin TQFP package (14 x 14 mm body, 0.5 mm pitch) requires a 4-layer PCB with continuous power and ground planes under the device to manage simultaneous switching noise. Route JTAG signals (TDI/TDO/TMS/TCK) as a daisy chain with 10 kΩ pull-ups on TMS and TCK, and place a 4.7 kΩ series terminator on TDO if the chain length exceeds 100 mm. For ISP chains longer than 4 devices, use a star topology to avoid signal integrity issues during programming.
Estimated: the TQFP-100 has a θJA of approximately 35-40 °C/W on a 4-layer JEDEC test board. At maximum operating ambient (70 °C commercial) and worst-case power dissipation of ~1 W (core + I/O), junction temperature rise is 35-40 °C above ambient, leaving 35-40 °C margin to the datasheet maximum Tj of 150 °C. For enclosed industrial enclosures with ambient above 50 °C, add thermal vias under the exposed pad region and ensure minimum 50 mm² of copper pour on both top and bottom layers.
Do not leave JTAG pins floating: TCK and TMS must be pulled to logic high through 10 kΩ resistors to keep the TAP controller in a defined state during power-up, otherwise the device may enter random JTAG states. VCCIO must ramp up before or simultaneously with VCCINT to prevent I/O latch-up; use a common power-sequencer IC or RC delay on the VCCINT rail if independent rails are used. Never exceed the maximum JTAG TCK frequency of 10 MHz for in-system programming.
Compliance Information
RoHS compliance indicated by the -N suffix per Altera/Intel ordering information. REACH SVHC declaration available from Intel product compliance page. Not AEC-Q100 qualified - this is a commercial-grade part intended for industrial and consumer applications. Conflict-minerals declaration compliant per Intel Conflict-Free Smelter Program.
