EPM5032DC-20 vs EPM5032DI-20 Comparison
Detailed side-by-side comparison of EPM5032DC-20 by Intel and EPM5032DI-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5032DC-20
EPM5032DC-20 - 600-Gate, 32-Macrocell MAX 5000 CPLD DIP-20 | Intel
EPM5032DC-20 ObsoleteIntel
EPM5032DI-20
EPM5032DI-20 - 32-Macrocell MAX 5000 EPLD, 62.5MHz, DIP-20 | Intel
EPM5032DI-20 ObsoleteSpecification Comparison
| Parameter | EPM5032DC-20 | EPM5032DI-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.05 | $8.75 |
| Product Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Programmable Technology | UV-Erasable / OTP EPROM | β |
| Usable Gates | 600 | β |
| Macrocells | 32 | 32 |
| Maximum Frequency (fCNT) | 71.4 MHz | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Speed Grade | -20 | β |
| Supply Voltage (VCC) | 5 V | β |
| Package | 20-pin DIP (Windowed Ceramic, 0.3" wide) | Ceramic DIP-20 (windowed, UV-erasable) |
| Mounting Type | Through-Hole | β |
| Logic Blocks | 4 Logic Array Blocks (LABs) | β |
| I/O Pins | [DATA_NEEDED: I/O pin count for DIP-20 variant] | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | Industrial (per 'I' suffix) |
| RoHS Status | Compliant (per IC-Components listing) | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Lead Free | [DATA_NEEDED: confirmed lead-free] | β |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | β |
| Programming Method | Altera MAX+PLUS II / Quartus (legacy support) | β |
| Family | β | MAX 5000 (Altera legacy EPLD) |
| Architecture | β | CMOS PAL-type EPLD with PIA |
| Dedicated Inputs | β | 7 |
| Bidirectional I/O Pins | β | 16 |
| Product Terms | β | 320 (maximum) |
| Flip-Flops | β | 16 (one per macrocell) |
| Maximum Clock Frequency | β | 62.5 MHz |
| Pin-to-Pin Delay | β | 20 ns (speed grade -20) |
| Programming | β | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | β | Altera MAX+PLUS II (legacy) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |