EPM5032DC-20 vs EPM5032DI-25 Comparison
Detailed side-by-side comparison of EPM5032DC-20 by Intel and EPM5032DI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5032DC-20
EPM5032DC-20 - 600-Gate, 32-Macrocell MAX 5000 CPLD DIP-20 | Intel
EPM5032DC-20 ObsoleteAltera
EPM5032DI-25
EPM5032DI-25 - 32-Macrocell UV PLD, 25ns, CMOS | Altera MAX 5000
EPM5032DI-25 NrndSpecification Comparison
| Parameter | EPM5032DC-20 | EPM5032DI-25 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.05 | $18.20 |
| Product Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Programmable Technology | UV-Erasable / OTP EPROM | β |
| Usable Gates | 600 | β |
| Macrocells | 32 | 32 |
| Maximum Frequency (fCNT) | 71.4 MHz | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Speed Grade | -20 | β |
| Supply Voltage (VCC) | 5 V | β |
| Package | 20-pin DIP (Windowed Ceramic, 0.3" wide) | Ceramic DIP, windowed (UV-erasable) |
| Mounting Type | Through-Hole | β |
| Logic Blocks | 4 Logic Array Blocks (LABs) | β |
| I/O Pins | [DATA_NEEDED: I/O pin count for DIP-20 variant] | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| RoHS Status | Compliant (per IC-Components listing) | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Lead Free | [DATA_NEEDED: confirmed lead-free] | β |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | β |
| Programming Method | Altera MAX+PLUS II / Quartus (legacy support) | β |
| Family | β | MAX 5000 |
| Architecture | β | PAL-type, CMOS, AND-OR sum-of-products |
| Product Terms | β | 320 |
| Logic Gates | β | [DATA_NEEDED: equivalent gate count] |
| Dedicated Inputs | β | 7 |
| Bidirectional I/O Pins | β | 16 |
| Total Array Inputs | β | 24 |
| Registered Outputs | β | 16 |
| Global Clocks | β | 1 |
| Propagation Delay (tPD) | β | 25 ns |
| Maximum Clock Frequency (fMAX) | β | 62.5 MHz |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |
| Pin Count | β | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | β | TTL-compatible |
| Programmability | β | UV-erasable, EPROM-based |
| Development Tool | β | MAX+PLUS II / A+PLUS |
| Lifecycle | β | Not Recommended for New Designs (NRND) |