EPM5032PC-15 vs EPM5032LC-15 Comparison

Detailed side-by-side comparison of EPM5032PC-15 by Altera and EPM5032LC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5032LC-15

EPM5032LC-15 - MAX 5000 CPLD, 32 Macro Cells, 83.3 MHz | Altera

EPM5032LC-15 Obsolete

Specification Comparison

Parameter EPM5032PC-15 EPM5032LC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.10 $8.20
Device Family MAX 5000 β€”
Device Type EPLD (Erasable PLD) β€”
Macro Cells 32 β€”
Usable Gates 600 600
Logic Elements / LABs 1 LAB (4 macrocells per group) β€”
Propagation Delay (tPD) 15 ns β€”
Maximum Internal Frequency 76.9 MHz (some sources list 83.3 MHz) β€”
Operating Voltage (VCC) 5 V (typ.) β€”
Technology Node 0.8 micron CMOS β€”
Configuration Memory UV-Erasable EPROM β€”
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 16
Total Array Inputs 24 β€”
Package 28-pin PDIP (PC suffix = windowed CerDIP) JLCC-28 (windowed ceramic)
Pin/Package Suffix PC = Windowed Ceramic DIP β€”
Speed Grade 15 (15 ns tPD) β€”
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Programming Tool Altera Logic Programmer + MAX+plus II β€”
RoHS Status Non-compliant (CerDIP window, contains Be) Non-compliant (contains Pb, ceramic-windowed package)
Lead-Free No β€”
Mounting Type Through-Hole (DIP) β€”
Family β€” MAX 5000 EPLD
Architecture β€” PAL-type AND/OR with PIA
Macrocells β€” 32
Logic Array Blocks (LABs) β€” 4
Maximum Operating Frequency β€” 83.3 MHz
Pin-to-Pin Delay (tPD) β€” 15 ns
Supply Voltage (VCC) β€” 5 V (4.75 V to 5.25 V)
Technology β€” CMOS EPROM, 1.0 um process
Programmability β€” UV-Erasable / OTP

Datasheets & Resources

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