EPM5032PC-15 - 32-Macrocell MAX 5000 CPLD, 15ns PDIP-28 | Altera
MPN: EPM5032PC-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.2 | $152.00 |
| 100 | $12.4 | $1,240.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.1 | $8,100.00 |
EPM5032PC-15 Overview
What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable integrated circuit containing multiple PAL-style macrocell arrays interconnected by a central Programmable Interconnect Array (PIA). CPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and full FPGAs, offering deterministic timing, instant-on behavior from on-chip EPROM/EEPROM, and high-drive I/O suitable for bus-interface glue logic. They belong to the broader Programmable Logic Device (PLD) -> Logic IC -> semiconductor taxonomy and are commonly used as interface bridges, state machines, and address decoders in legacy and industrial designs.
The EPM5032PC-15 implements 7 dedicated inputs and 16 bidirectional I/O pins (total 24 array inputs) routed through the PIA to 32 macrocells. The "PC-15" speed grade sets the propagation delay (tPD) at 15 ns from any input or feedback path to any output, with a maximum toggle frequency above 76.9 MHz as captured by the FindIC datasheet index. Macrocell features include configurable D/T/JK flip-flops, asynchronous clear/preset, and dedicated output enable logic, supporting synchronous state-machine design without external glue logic.
The MAX 5000 family employs UV-erasable EPROM cells for configuration retention, allowing unlimited reprogramming cycles after window erasure. Programming is performed via the Altera Logic Programmer card and the legacy MAX+plus II (or Quartus) development toolchain. The device is offered in commercial operating temperature grades only, with industrial-grade coverage limited to the wider EPM5032 family.
Typical applications include legacy PC/AT address decoding, ISA bus interface glue logic, industrial control state machines, and pin-compatible upgrades of 7400-series TTL/CMOS designs. The 15 ns tPD comfortably meets the 8 MHz ISA bus cycle timing and 10 MHz VESA local-bus timing without wait-state insertion.
When designing with this device, ensure the target PCB footprint accepts a 0.600-inch wide 28-pin PDIP; for surface-mount migration, see the EPM5032DC/-15 variant in PLCC-28. Designers migrating modern designs should consider the Altera MAX II family (EPM240, EPM570) for lower power, instant-on flash-based configuration, and free Quartus II support.
This page synthesizes distributor availability, speed-grade alternatives from the same MAX 5000 family, and practical design notes not found in the original datasheet front matter.
Drop-in alternatives for EPM5032PC-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5032PC-15 (same form factor and footprint) — differing in Package, Device Type, Supply Voltage (VCC), Mounting Type, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5032PC-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.05 / Unit
View Datasheet →EPM5032PC-25
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPM5032LC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$8.2 / Unit
View Datasheet →EPM5032LC-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$8.4 / Unit
View Datasheet →EPM5032DC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EPM5032PC-15 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 5000 |
| Device Type | EPLD (Erasable PLD) |
| Macro Cells | 32 |
| Usable Gates | 600 |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | 5 V (typ.) |
| Technology Node | 0.8 micron CMOS |
| Configuration Memory | UV-Erasable EPROM |
| Dedicated Inputs | 7 |
| Bidirectional I/O Pins | 16 |
| Total Array Inputs | 24 |
| Package | 28-pin PDIP (PC suffix = windowed CerDIP) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP |
| Speed Grade | 15 (15 ns tPD) |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Tool | Altera Logic Programmer + MAX+plus II |
| RoHS Status | Non-compliant (CerDIP window, contains Be) |
| Lead-Free | No |
| Mounting Type | Through-Hole (DIP) |
EPM5032PC-15 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell bank) |
| Pin 17 | IN — Dedicated input (to PIA) |
| Pin 18 | IN — Dedicated input (to PIA) |
| Pin 19 | IN — Dedicated input (to PIA) |
| Pin 20 | IN — Dedicated input (to PIA) |
| Pin 21 | IN — Dedicated input (to PIA) |
| Pin 22 | IN — Dedicated input (to PIA) |
| Pin 23 | IN — Dedicated input (to PIA) |
| Pin 24 | GND — Ground (0 V) |
| Pin 25 | VCC — Positive supply (5 V) |
| Pin 26 | OE — Output enable (global, programmable polarity) |
| Pin 27 | CLK — Global clock input (to macrocell flip-flops) |
| Pin 28 | VPP/PRG — Programming voltage / mode select |
Typical Applications
EPM5032PC-15 is suitable for 6 applications: Legacy ISA Bus Address Decoding, VESA Local-Bus Interface Glue Logic, Industrial Control State Machines, 7400-Series TTL Replacement in Maintenance Designs, PC/AT Motherboard Chip Select Generation, Retro-Computing Hardware Emulation.
Legacy ISA Bus Address Decoding
The EPM5032PC-15 fits legacy ISA bus address-decoding applications because its 15 ns tPD easily meets the 8 MHz ISA cycle time without wait states. Its 32 macrocells provide sufficient capacity for a full 24-bit ISA address decoder with chip-select and command-signal generation. Combined with the 5 V VCC tolerance and 16 mA sink capability of the MAX 5000 family I/O, the part directly drives ISA bus control lines without external buffers. Compared to discrete 74LS138/139 decoders, one EPM5032PC-15 can replace three to four SSI/MSI packages while remaining transparent to BIOS POST routines.
Recommended
VESA Local-Bus Interface Glue Logic
The EPM5032PC-15 supports VESA local-bus (VLB) interface glue logic through its 15 ns tPD that meets the 33 MHz VLB-to-ISA bridge cycle budget. The 32 macrocells accommodate a typical VESA-to-ISA bridge controller (address latch, byte enables, ready-signal generation, and DMA arbitration) within a single device. Its instant-on UV-EPROM configuration ensures the VESA bridge is operational before the host CPU begins its first bus cycle, eliminating BIOS POST compatibility issues. The 5 V-tolerant I/O buffers drive VLB signal lines without external transceivers in most 3-slot VLB implementations.
Recommended
Industrial Control State Machines
The EPM5032PC-15 fits industrial control state-machine applications due to its 32 macrocells (each with configurable D/T/JK flip-flop), deterministic 15 ns clock-to-output, and 7 dedicated inputs for asynchronous event handling. Engineers use the MAX 5000 family for PLC scan-engine, sequencer, and pulse-train generation because its EPROM-based configuration is immune to power-cycle corruption in noisy factory environments. The 5 V supply and CMOS low-power consumption (typically under 200 mW at full toggle) suit 24 V industrial backplanes with linear regulation. The windowed CerDIP package allows unlimited in-circuit reprogramming during commissioning.
Recommended
7400-Series TTL Replacement in Maintenance Designs
The EPM5032PC-15 serves as a 7400-series TTL replacement in maintenance and refurbishment designs because one device can replace 10 to 20 SSI/MSI 74LS/74HC packages while reducing board area and power consumption. Its macrocell flip-flops emulate 74LS374 latches, 74LS244/245 buffers, and 74LS138/139 decoders without external glue. The 15 ns tPD equals or beats 74LS series propagation delays, preserving timing margins in existing PCB layouts. The windowed CerDIP package allows field re-programming to adapt legacy boards to updated peripheral interfaces without board rework.
Recommended
PC/AT Motherboard Chip Select Generation
The EPM5032PC-15 fits PC/AT motherboard chip-select generation because its 32 macrocells cover the full set of XT/AT peripheral select signals (DRAM, ROM, ISA slot, DMA, interrupt, keyboard controller, real-time clock) in a single device. The 15 ns tPD ensures chip-select lines stabilize well before the ISA cycle's command strobe, eliminating address-to-write contention. The 5 V supply matches legacy AT power rails directly, and the dedicated input pins accept latched address bits without external buffering. UV-EPROM configuration survives AT power-on sequencing without bootloader dependency.
Recommended
Retro-Computing Hardware Emulation
The EPM5032PC-15 supports retro-computing hardware emulation projects including 1980s arcade board replacements, 8-bit microcomputer peripheral cards, and discrete CPU glue-logic replicas. Hobbyists use the MAX 5000 family because the original-era datasheets, programmer hardware, and Quartus legacy libraries remain available through the Altera University Program archives. The 15 ns tPD faithfully replicates 6502/Z80 bus timing, while the 32 macrocells accommodate a full address decoder plus interrupt controller in one chip. The windowed CerDIP package gives authentic retro aesthetics for visible-installation projects.
Recommended
Recommended Products Summary
Engineering reference data for EPM5032PC-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5032PC-20 | EPM5032PC-25 | EPM5032LC-15 | EPM5032LC-20 | EPM5032DC-15 |
|---|---|---|---|---|---|---|
| Package | 28-pin PDIP (windowed CerDIP) | 28-pin PDIP (windowed CerDIP) - same | 28-pin PDIP (windowed CerDIP) - same | 28-pin PDIP (windowed CerDIP) - same family | 28-pin PDIP (windowed CerDIP) - same family | 28-pin PDIP (CerDIP) - same family |
| Brand | Altera (now Intel FPGA) | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 15 ns | 20 ns | 25 ns | 15 ns | 20 ns | 15 ns |
| Macro Cells | 32 | 32 | 32 | 32 | 32 | 32 |
| Usable Gates | 600 | 600 | 600 | 600 | 600 | 600 |
| Configuration Memory | UV-EPROM (windowed) | UV-EPROM (windowed) | UV-EPROM (windowed) | UV-EPROM (windowed) | UV-EPROM (windowed) | UV-EPROM (windowed) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Operating Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
Key Differentiators
- Fastest speed grade in the MAX 5000 family windowed-DIP lineup (vs EPM5032PC-20)
- Windowed CerDIP package allows unlimited field reprogramming (vs EPM5032DM (Cerdip, non-windowed) / EPM5016 family)
- 32 macrocells accommodate full PC/AT chip-select decoding in a single device (vs EPM5016PC-1 (16 macrocells))
Design Notes
Estimated: EPM5032PC-15 is RoHS-non-compliant because the CerDIP window contains beryllium and the lead-frame finish contains lead. Do not specify this part for any EU or RoHS-bound end product. For new designs, use a MAX II (EPM240T100C5N) or MAX V (5M240ZT100C5N) flash-based CPLD in TQFP-100. The windowed CerDIP also requires UV erasure (~30 minutes under 254 nm at 20 mW/cm^2) before reprogramming; one-time-programmable (OTP) plastic DIP variants in the MAX 5000 family do not exist.
Estimated: At 76.9 MHz full toggle on all 16 outputs into 50 pF loads, the EPM5032PC-15 consumes approximately 200 to 250 mW from its 5 V supply, drawing ~40 to 50 mA. Add a 0.1 uF ceramic bypass capacitor within 5 mm of the VCC pin (pin 25) and a bulk 10 uF tantalum on the 5 V rail. The device has no internal power-on-reset; the first clock cycles after VCC rise may produce spurious outputs, so external reset circuitry or a pull-up on the global OE pin (pin 26) is recommended for deterministic startup.
The 28-pin PDIP footprint is 0.600 inch wide with 0.100 inch (2.54 mm) pin pitch and 0.018 inch (0.46 mm) through-hole pads. Reserve at least 0.050 inch clearance between pin rows and adjacent traces for wave-solder manufacturing. Place a ground plane on the solder side directly under the IC to provide a low-impedance return path for the high-di/dt switching transients typical of 16 simultaneously-toggling outputs. Route all 16 I/O traces with matched impedance (~50 ohm) if any trace exceeds 50 mm to prevent reflection-induced timing violations.
Estimated: The EPM5032PC-15 in 28-pin CerDIP has a theta_JA of approximately 65 C/W (still air) due to the ceramic package's lower thermal conductivity than plastic. Maximum junction temperature is 150 C (commercial). At 250 mW dissipation, the junction-to-ambient rise is ~16 C, so the part is thermally safe in any reasonable airflow environment. The windowed CerDIP can, however, lose its hermetic seal above 200 C during soldering; use a sockets (e.g., 3M Textool 28-pin DIP) to avoid exposing the part to wave-solder thermal profiles.
Compliance Information
CerDIP windowed package contains beryllium (Be) and lead (Pb) in the lead-frame finish, making the part RoHS non-compliant. The MAX 5000 family was discontinued before the 2006 RoHS deadline. AEC-Q100 qualification does not apply to this commercial-grade legacy EPLD; no industrial-temperature (-40C to +85C) variant exists in the MAX 5000 family. Halogen-free status unknown. No REACH SVHC disclosure available for this legacy part.
