EPM5032PC-15 vs EPM5032LC-20 Comparison
Detailed side-by-side comparison of EPM5032PC-15 by Altera and EPM5032LC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032PC-15 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.10 | $8.40 |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | β |
| Macro Cells | 32 | β |
| Usable Gates | 600 | 600 gates |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | β |
| Propagation Delay (tPD) | 15 ns | 20 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | β |
| Operating Voltage (VCC) | 5 V (typ.) | β |
| Technology Node | 0.8 micron CMOS | β |
| Configuration Memory | UV-Erasable EPROM | β |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | β |
| Package | 28-pin PDIP (PC suffix = windowed CerDIP) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | β |
| Speed Grade | 15 (15 ns tPD) | -20 (20 ns pin-to-pin) |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to +70 Β°C (commercial; -55 Β°C to +125 Β°C military per /883B variants) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | β |
| RoHS Status | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status] |
| Lead-Free | No | β |
| Mounting Type | Through-Hole (DIP) | Surface Mount |
| Product Type | β | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Macrocells | β | 32 |
| Logic Blocks (LABs) | β | 1 |
| Maximum Frequency | β | 71.4 MHz |
| Supply Voltage (VCC) | β | 5 V Β±5% |
| Total Inputs | β | 24 |
| Output Functions | β | 16 |
| Product Terms per Output | β | 16 |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA) |
| MSL Level | β | [DATA_NEEDED: MSL] |