EPM5064JC-2 vs EPM5064LC-2 Comparison

Detailed side-by-side comparison of EPM5064JC-2 by Altera and EPM5064LC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5064JC-2

EPM5064JC-2 - 64-Macrocell UV PLD, 45ns | Altera MAX 5000

EPM5064JC-2 Obsolete
Altera
EPM5064LC-2

EPM5064LC-2 - 64-Macrocell MAX 5000 CPLD, 45ns, PLCC44 | Altera

EPM5064LC-2 Obsolete

Specification Comparison

Parameter EPM5064JC-2 EPM5064LC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $23.10 $8.40
Family MAX 5000 β€”
Macrocells 64 64
Logic Array Blocks (LABs) 4 4
Propagation Delay (tPD) 45 ns 45 ns
Maximum Clock Frequency (fMAX) 50 MHz β€”
Usable Gates 1250 β€”
Dedicated Inputs 7 β€”
I/O Pins 28 β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Technology CMOS, UV-erasable EPROM β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 4.75 V to 5.25 V (5 V nominal)
Programming Method UV-erase + EPROM programmer (not ISP) Altera byte-wide / JTAG programmer
Package 28-pin CLCC (J-lead, ceramic, windowed) PLCC-44 (J-Lead, plastic)
Operating Temperature [DATA_NEEDED: commercial or industrial grade] -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
Compliance RoHS status unknown (ceramic/J-lead windowed part, legacy product) β€”
Device Family β€” MAX 5000
Product Type β€” CPLD (Complex Programmable Logic Device)
Logic Elements per LAB β€” 16
Number of Inputs β€” 36 (7 dedicated + 28 I/O)
Number of I/O Pins β€” 28
Number of Flip-Flops β€” 28
Maximum Internal Frequency β€” 40 MHz
Process Technology β€” CMOS, OTP EPROM (UV-erasable base)
Programmable Polarity β€” Yes
Programmable Output Enable β€” Yes, per macrocell
Mounting Type β€” Surface Mount
RoHS Status β€” [DATA_NEEDED: not specified in source]

Datasheets & Resources

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