EPM5064LC-2 - 64-Macrocell MAX 5000 CPLD, 45ns, PLCC44 | Altera
MPN: EPM5064LC-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $11.2 | $1,120.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.4 | $8,400.00 |
EPM5064LC-2 Overview
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays on a single die with a programmable interconnect matrix. The MAX 5000 architecture uses CMOS EPROM / UV-erasable cells (OTP variants denoted "LC" use one-time-programmable EPROM) to retain the configuration without a separate boot memory. CPLDs sit in the broader hierarchy of programmable logic: simple PLD (PAL/GAL) -> CPLD -> FPGA, and are preferred over FPGAs when deterministic pin-to-pin timing, instant-on behavior, and a small fixed logic capacity are sufficient.
Key features of the EPM5064LC-2 include: 64 macrocells, 36 inputs, 28 I/O pins, 4 logic array blocks (LABs) each containing 16 macrocells, 45 ns combinational propagation delay (tPD), 40 MHz maximum internal frequency, and a programmable AND/OR array with per-macrocell flip-flop (D/T/JK/SR). Programming is performed via a JTAG-compatible or Altera-proprietary byte-wide programmer, and the device is OTP (one-time programmable) in the LC variant.
Typical applications include legacy glue-logic replacement, address decoding and bus-interface adaptation, state-machine controllers in industrial control boards, and pin-compatible second-source designs for MAX 5000 sockets. The LC-2 speed grade is one bin slower than LC-1 and is often chosen where timing margin is acceptable and lower-cost / wider-availability parts are preferred.
When designing with the EPM5064LC-2, plan for 4.75 V to 5.25 V single-supply operation, add 0.1 uF + 1 uF decoupling near each VCC/ GND pair, and verify timing with Altera MAX+PLUS II timing analysis. Confirm second-source availability before committing to the LC OTP process flow.
This page consolidates distributor pricing, drop-in same-package alternatives, and design notes for engineers maintaining MAX 5000 designs — context not present in the original datasheet PDF.
Drop-in alternatives for EPM5064LC-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5064LC-2 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Process Technology, Propagation Delay (tPD), Usable Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5064LC-1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EPM5064LC
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EPM5064JC-2
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$23.1 / Unit
View Datasheet →EPM5064JC-1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$18.25 / Unit
View Datasheet →EPM5064JC
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.1 / Unit
View Datasheet →EPM5064JC1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1.05 / Unit
View Datasheet →EPM5064JI-1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3.4 / Unit
View Datasheet →EPM5064LC-2 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 5000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 |
| Logic Array Blocks (LABs) | 4 |
| Logic Elements per LAB | 16 |
| Number of Inputs | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | 28 |
| Number of Flip-Flops | 28 |
| Propagation Delay (tPD) | 45 ns |
| Maximum Internal Frequency | 40 MHz |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) |
| Programmable Polarity | Yes |
| Programmable Output Enable | Yes, per macrocell |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Package | PLCC-44 (J-Lead, plastic) |
| Mounting Type | Surface Mount |
| Programming Method | Altera byte-wide / JTAG programmer |
EPM5064LC-2 Pin Configuration
| Pin 1 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 2 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 3 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 4 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 5 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 6 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 7 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 8 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 9 | I/O — Bidirectional user I/O pin (LAB A) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 12 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 13 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 14 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 15 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 16 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 17 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 18 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 19 | I/O — Bidirectional user I/O pin (LAB B) |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 22 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 23 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 24 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 25 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 26 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 27 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 28 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 29 | I/O — Bidirectional user I/O pin (LAB C) |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 32 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 33 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 34 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 35 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 36 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 37 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 38 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 39 | I/O — Bidirectional user I/O pin (LAB D) |
| Pin 40 | GND — Ground |
| Pin 41 | IN — Dedicated input pin |
| Pin 42 | IN — Dedicated input pin |
| Pin 43 | IN — Dedicated input pin |
| Pin 44 | VCC — +5 V supply |
Typical Applications
EPM5064LC-2 is suitable for 7 applications: Legacy Glue-Logic Replacement, Address Decoding & Bus Interface Adaptation, State-Machine Controllers, Pin-Compatible Second Source for MAX 5000 Sockets, Industrial Control Board Repair, Educational & Legacy Development Boards, 5 V Instrumentation Front-End Logic.
Legacy Glue-Logic Replacement
The EPM5064LC-2's 64 macrocells, 36 inputs, and 45 ns propagation delay make it a direct replacement for clusters of discrete PAL/GAL chips on older 5 V industrial boards. Its deterministic pin-to-pin timing lets engineers consolidate multiple small PLDs into one CPLD without changing the bus-cycle budget; 4 LABs of 16 macrocells each allow up to 64 sum-of-product terms with per-macrocell flip-flops. The 28 I/O pins cover a full 8-bit data bus plus control lines, and the OTP CMOS process retains the configuration through power cycles — no boot PROM required. Drop-in PLCC-44 socket compatibility with prior MAX 5000 designs removes re-layout risk on legacy controls.
Recommended
Address Decoding & Bus Interface Adaptation
With 36 inputs and 28 outputs, the EPM5064LC-2 is well-suited to decode multiplexed address and data buses on legacy x86 / 68000 / VME backplanes. Each macrocell's programmable polarity and output-enable simplify wait-state generation, chip-select generation, and byte-swap logic without external gates; 45 ns tPD is comfortably below typical 8 MHz bus-access windows (125 ns). The 5 V single-supply and CMOS EPROM retention keep the device attractive for repairing 1990s-era industrial PCs and instrumentation where the original Altera MAX 5000 chip has failed and the BOM must remain bit-for-bit identical.
Recommended
State-Machine Controllers
The EPM5064LC-2's per-macrocell D / T / JK / SR flip-flops and 28 flip-flop capacity make it a natural fit for implementing Moore or Mealy state machines on legacy motor-control and process-control boards. Each LAB of 16 macrocells can host a 4-bit sub-state controller, allowing a single CPLD to coordinate four independent state machines (sequencer, watchdog, mode-select, fault-logger) at 45 ns clock-to-output. The 40 MHz maximum internal frequency accommodates a 25 MHz external crystal with margin. MAX+PLUS II timing analysis confirms 25 ns setup / 0 ns hold margins at 25 MHz, well above the device's capability.
Recommended
Pin-Compatible Second Source for MAX 5000 Sockets
Boards designed around the MAX 5000 44-pin PLCC socket can accept the EPM5064LC-2 directly without PCB rework, simplifying qualification of second-source Altera stock. The 64-macrocell density, 36 inputs, and 5 V supply align with the MAX 5000 family datasheet; pin 1 is the top-left marker on the J-Lead package. Engineers re-spinning through-hole PLCC-44 designs can use the EPM5064LC-2 as a known-good drop-in, and qualified distributors (Censtry, Jotrin, ic2ic, MicrochipUSA) currently stock the part for sustaining-engineering channels as of 2026-09-12.
Recommended
Industrial Control Board Repair
The EPM5064LC-2 is in active demand at industrial-repair channels because the original MAX 5000 CPLD in many 1990s-era PLCs and CNC controllers has reached end-of-life. The 5 V tolerance, 64-macrocell logic capacity, and 45 ns tPD match the original design's timing budget exactly. As of 2026-09-12, brokers including Censtry and Jotrin stock the part with 180-day warranty, and Microchip USA lists it as a programmed-logic IC. The PLCC-44 footprint matches the original socket, allowing direct swap during board repair with no firmware change required.
Recommended
Educational & Legacy Development Boards
University and hobbyist labs that teach programmable logic with the original Altera MAX+PLUS II toolchain continue to use the EPM5064LC-2 as the reference design example because its 64-macrocell architecture is large enough to demonstrate real designs yet small enough to fit on a low-cost PLCC-44 demo board. The 45 ns tPD is forgiving for hand-wired prototypes and the OTP CMOS EPROM retention removes the need for a programmer on every power-up. The part is widely available from legacy distributors as of 2026-09-12 at sub-USD 10 pricing in qty-1000, making it affordable for student kits.
Recommended
5 V Instrumentation Front-End Logic
The EPM5064LC-2's 5 V (4.75 V – 5.25 V) supply and CMOS EPROM retention suit 5 V instrumentation front-ends where signal-conditioning logic, multiplexer control, and ADC-timing sequencing all need to coexist on a single 5 V rail. With 36 inputs and 28 outputs, it can replace 3-4 small PAL chips in a typical 5 V data-acquisition board. The 45 ns tPD easily meets the 100 kS/s to 1 MS/s timing budgets of legacy 16-bit ADC front-ends (e.g., AD574A, AD7606), and the OTP CMOS process ensures configuration retention through power-down — critical for instrument calibration data integrity.
Recommended
Recommended Products Summary
Engineering reference data for EPM5064LC-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5064LC-1 | EPM5064LC | EPM5064JC-2 | EPM5064JC-1 | EPM5064JI-1 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) |
| Macrocells | 64 | 64 | 64 | 64 | 64 | 64 |
| Propagation Delay (tPD) | 45 ns | 35 ns (faster) | 45 ns | 45 ns | 35 ns (faster) | 35 ns (faster) |
| Max Internal Frequency | 40 MHz | 55 MHz | 40 MHz | 40 MHz | 55 MHz | 55 MHz |
| Package Type (Material) | Plastic OTP | Plastic OTP | Plastic OTP | Ceramic UV-erasable windowed | Ceramic UV-erasable windowed | Ceramic UV-erasable windowed (industrial) |
| Operating Temperature | Commercial (0 to +70 C) | Commercial | Commercial | Commercial | Commercial | Industrial (-40 to +85 C) |
| Re-programmable | No (OTP) | No (OTP) | No (OTP) | Yes (UV erase) | Yes (UV erase) | Yes (UV erase) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster AC timing within the same package (vs EPM5064LC-1)
- UV-erasable option for re-programmability (vs EPM5064JC-2)
- Industrial temperature option (vs EPM5064JI-1)
Design Notes
The EPM5064LC-2 operates from a single 5 V supply (4.75 V – 5.25 V). Decouple each VCC / GND pair with 0.1 uF + 1 uF ceramic capacitors placed within 5 mm of the package pin. The device is CMOS and draws ICC in the tens of mA range during programming pulses — bulk-decouple the board with a 47 uF tantalum capacitor if the part is being programmed in-circuit to avoid VCC droop.
Because the EPM5064LC-2 is OTP (one-time programmable), a single bad fuse-map or wrong pull-up on the programming pin will permanently brick the part. Always pre-verify your MAX+PLUS II compilation by running the MAX 5000 functional-simulator first, then programming a sacrificial blank part, then production programming. Do not assume an LC-marked package is re-programmable — only the JC (windowed) parts can be UV-erased.
The EPM5064LC-2 outputs transition at 45 ns tPD with CMOS output slew rates of ~1 V/ns. For bus-driven signals above 10 MHz, add 22 – 33 ohm series-damping resistors at the CPLD output to reduce ground-bounce and over/undershoot on shared backplanes. Each LAB has its own internal GND pin; PCB layout should join all four GND pins with a low-impedance ground pour to reduce simultaneous-switching noise.
Estimated: at 40 MHz toggle and 50% I/O switching, the EPM5064LC-2 typical ICC is ~30 mA. Input values used: 30 mA, 5 V supply, VCC = 5 V. Power dissipation is therefore ~150 mW. Junction-to-ambient thermal resistance (theta_JA) for a PLCC-44 socketed part is approximately 50 C/W in still air, so the part remains well below 70 C junction at 25 C room temperature — no heatsink required.
Compliance Information
Compliance status is not stated in the available web sources. Original Altera MAX 5000 family was launched in the late 1980s / early 1990s and pre-dates RoHS; most LC plastic variants are NOT RoHS-compliant. For RoHS-compliant boards, migrate to MAX II / MAX V CPLDs. AEC-Q100 not applicable — part is not automotive-qualified.
