EPM5064JC vs EPM5064LC Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5064LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5064LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $7.10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | β |
| Usable Gates | 1,250 (approx.) | 1.25K |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | PLCC-44 (LCC-44, J-lead) |
| Mounting Type | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.75 V to 5.25 V |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0C to +70C (Commercial) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Programming Type | β | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | β | 64 |
| Logic Array Blocks (LABs) | β | 4 |
| Propagation Delay (tPD) | β | 55 ns |
| Total Inputs | β | 36 (7 dedicated + 29 I/O) |
| I/O Pins | β | 28 bidirectional + 4 dedicated input |
| Process Technology | β | CMOS EPROM |
| Lead Free | β | [DATA_NEEDED: lead-free status] |