EPM5064LC - 64-Macrocell MAX 5000 CPLD, 55ns, 5V | Altera
MPN: EPM5064LC ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
EPM5064LC Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile, deterministic-logic semiconductor that sits between discrete 74-series glue logic and higher-density FPGAs. It belongs to the taxonomy programmable logic device (PLD) -> CPLD -> MAX family -> MAX 5000 series. CPLDs provide predictable timing through a fixed AND/OR architecture with a Programmable Interconnect Array (PIA), making them ideal for bus decoding, address mapping, state-machine control, and I/O expansion in systems that need instant-on behavior without external boot memory.
Key features of the EPM5064LC include 64 macrocells organized into 4 Logic Array Blocks (LABs), 36 total inputs (7 of them dedicated), 28 bidirectional I/O pins, and 4 user I/O pins, all accessible through the J-lead PLCC-44 footprint. It supports TTL-level interfaces, in-system programmability via the Altera MAX+PLUS II / MAX+PLUS II baseline toolchain, and offers 100% generic testability. The device is rated for the commercial 0C to +70C operating range.
Architecturally, the EPM5064LC combines four LABs interconnected by a global PIA. Each macrocell contains a programmable AND/OR array, a flip-flop, and a tri-state output buffer, allowing combinatorial or registered logic. The EPROM-based interconnect provides non-volatile configuration with zero standby power for the routing fabric, while the CMOS output stage supports 24 mA drive for LED and bus-driving applications.
Typical applications include legacy peripheral glue logic, 5V ISA bus decoding, address decoding in embedded 80x86 and 68K systems, state-machine control in industrial PLCs, and pin-compatible modernization of designs that originally used discrete PAL/GAL devices. The 44-pin PLCC package is also well suited to through-hole sockets for easy field replacement.
When designing with the EPM5064LC, ensure the supply rail is well decoupled with 0.1 uF ceramic and 10 uF tantalum capacitors placed within 25 mm of the VCC and GND pins. The device's OTP nature means firmware errors cannot be re-flashed in-circuit - use the windowed ceramic-package variant (EPM5064LC with quartz lid) for prototyping and the plastic OTP variant for production.
This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the same Altera MAX 5000 family, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EPM5064LC — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5064LC (same form factor and footprint) — differing in Package, Process Technology, Supply Voltage (VCC), Propagation Delay (tPD), Device Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5064LC-1
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPM5064LC-2
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPM5064JC
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EPM5064JC-1
✅ Drop-In✓ In Stock
$18.25 / Unit
View Datasheet →EPM5064JI-1
✅ Drop-In✓ In Stock
$3.4 / Unit
View Datasheet →EPM5064JC1
✅ Drop-In✓ In Stock
$1.05 / Unit
View Datasheet →EPM5064LC Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Programming Type | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | 64 |
| Usable Gates | 1.25K |
| Logic Array Blocks (LABs) | 4 |
| Propagation Delay (tPD) | 55 ns |
| Total Inputs | 36 (7 dedicated + 29 I/O) |
| I/O Pins | 28 bidirectional + 4 dedicated input |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (Commercial) |
| Package | PLCC-44 (LCC-44, J-lead) |
| Process Technology | CMOS EPROM |
| Mounting Type | Surface Mount |
EPM5064LC Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 18 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 19 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 20 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 23 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 24 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 25 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 26 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 27 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 28 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 29 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Pin 30 | GND — Ground |
| Pin 31 | IN — Dedicated input pin |
| Pin 32 | IN — Dedicated input pin |
| Pin 33 | IN — Dedicated input pin |
| Pin 34 | IN — Dedicated input pin |
| Pin 35 | VCC — +5V supply |
| Pin 36 | IN — Dedicated input pin |
| Pin 37 | IN — Dedicated input pin |
| Pin 38 | IN — Dedicated input pin |
| Pin 39 | IN — Dedicated input pin |
| Pin 40 | IN — Dedicated input pin |
| Pin 41 | IN — Dedicated input pin |
| Pin 42 | VCC — +5V supply |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
Typical Applications
EPM5064LC is suitable for 6 applications: Legacy ISA Bus Address Decoding, Embedded 80x86/68K Glue Logic Consolidation, Industrial PLC State Machine Controllers, Pin-Configurable Peripheral I/O Expansion, Bus Interface and Protocol Translation, LED Display Multiplex and Driver Control.
Legacy ISA Bus Address Decoding
The EPM5064LC is well suited to legacy 5 V ISA bus address decoding in industrial PCs and embedded single-board computers. Its 64 macrocells provide ample capacity to implement full 24-bit address decode with chip-select strobes for memory and peripheral windows. The 55 ns tPD easily meets the ISA bus 8 MHz clock period with timing margin to spare. Unlike discrete 74-series PAL/GAL decoders that consume board area, a single EPM5064LC replaces 4-6 decoder packages, freeing PCB real-estate for additional memory or peripheral functions. Place the device close to the bus buffers and use the dedicated input pins for the high-order address bits to minimize skew. Pin-compatible upgrade path to EPM5064LC-1 is available for systems that need faster decode to support higher bus speeds.
Recommended
Embedded 80x86/68K Glue Logic Consolidation
The EPM5064LC consolidates the half-dozen 74LS/74F glue-logic packages typically required around an 80x86 or 68K microprocessor into a single PLCC-44 device. Designers can implement address latching, interrupt encoding, wait-state generation, and bus arbitration inside one CPLD, shrinking the BOM and the PCB footprint. With 64 macrocells and 28 I/O pins, the EPM5064LC handles most 16-bit and many 32-bit designs. The OTP EPROM fabric ensures deterministic behavior on power-up with no boot memory required, critical for mission-critical industrial controllers. For prototyping, the EPM5064JC (windowed ceramic package) enables multiple erase/reprogram cycles; production should use the plastic LC variant for cost.
Recommended
Industrial PLC State Machine Controllers
The EPM5064LC is widely deployed in industrial PLC ladder-logic and state-machine controllers, where its non-volatile OTP configuration provides instant-on deterministic behavior after power cycling. With 64 macrocells organized into 4 LABs, the device can host several independent state machines for sequencing solenoids, motor starters, and indicator lamps. The 0-70C commercial temperature range suits enclosure-protected industrial environments, while the EPM5064JI-1 industrial variant extends coverage to -40C to +85C for outdoor cabinets. The 5 V supply aligns with legacy 24V->5V industrial backplanes. The 55 ns propagation delay is more than adequate for sub-microsecond ladder scan times typical of PLC execution loops.
Recommended
Pin-Configurable Peripheral I/O Expansion
The EPM5064LC enables designers to build a pin-configurable I/O expander for retro peripheral cards. With 28 bidirectional I/O pins, the device can map parallel-port data, control, and status registers into a memory-mapped window or implement an 8255-compatible PPI interface. The 7 dedicated inputs can capture bus-level control signals (RD, WR, CS, A0-A1) directly, while the macrocell flip-flops provide edge-detection and interrupt generation. The OTP nature prevents accidental firmware modification in the field, improving reliability. This application pattern is common in legacy data-acquisition cards and parallel-port industrial I/O modules.
Recommended
Bus Interface and Protocol Translation
The EPM5064LC bridges legacy 5 V parallel buses such as ISA, STD, or VME by implementing bus protocol translators between incompatible timing or voltage domains. Its 36 inputs and 28 outputs handle bus arbitration, data buffering control, and wait-state insertion in a single device. The 4 LABs enable modular design with each block handling a separate protocol layer. Combined with 5 V-tolerant TTL inputs and 24 mA drive outputs, the EPM5064LC can directly interface with TTL peripherals without external buffers. The 55 ns tPD provides comfortable margin for most 8 MHz and many 16 MHz bus standards, and the EPM5064LC-1 variant supports higher-speed buses.
Recommended
LED Display Multiplex and Driver Control
The EPM5064LC's 24 mA drive strength per output and 28 I/O pins make it ideal for multiplexed LED display controllers in scoreboards, instrumentation panels, and signage. Designers can implement 4-digit to 8-digit common-anode or common-cathode multiplex with BCD-to-7-segment decode and brightness PWM inside the 64 macrocells. The OTP fabric ensures the display pattern cannot be corrupted by voltage transients, a common failure mode in industrial environments. The 5 V supply aligns with standard LED driver transistors, and the PLCC-44 footprint allows socketed field replacement. For higher LED counts, multiple EPM5064LC devices can be cascaded with shared chip-select logic.
Recommended
Recommended Products Summary
Engineering reference data for EPM5064LC — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5064LC-1 | EPM5064LC-2 | EPM5064JC | EPM5064JC-1 | EPM5064JI-1 | EPM5064JC1 |
|---|---|---|---|---|---|---|---|
| Package | PLCC-44 (LCC-44) | PLCC-44 (LCC-44) - same | PLCC-44 (LCC-44) - same | PLCC-44 (LCC-44) - same | PLCC-44 (LCC-44) - same | PLCC-44 (LCC-44) - same | PLCC-44 (LCC-44) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 55 ns | 30 ns (faster) | 70 ns (slower) | 55 ns (same) | 30 ns | 30 ns | 30 ns |
| Macro Cells | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Usable Gates | 1.25K | 1.25K | 1.25K | 1.25K | 1.25K | 1.25K | 1.25K |
| Supply Voltage | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V | 4.75 V - 5.25 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Standard speed grade for cost-sensitive legacy designs (vs EPM5064LC-1)
- Plastic OTP package for high-volume production (vs EPM5064JC)
- Commercial temperature range only (vs EPM5064JI-1)
Design Notes
The EPM5064LC requires a clean 5 V supply within 4.75-5.25 V. Place a 10 uF tantalum bulk capacitor and a 0.1 uF ceramic decoupling capacitor within 25 mm of each VCC pin (pins 35 and 42). The PLCC-44 package has three GND pins (10, 21, 30) that must all be connected to a low-impedance ground plane to minimize ground bounce during simultaneous I/O switching. Estimated: with 28 I/O pins switching at 5 V and 24 mA drive, dynamic ground current spikes can exceed 200 mA; adequate decoupling is critical.
Use a socket (44-pin PLCC) during prototyping to allow easy replacement of OTP devices. The OTP EPROM fabric cannot be re-programmed in-circuit, so any logic error requires a new part. For production where field replacement is unlikely, direct soldering is acceptable. The J-lead PLCC-44 footprint has standard JEDEC land pattern dimensions - refer to Altera Application Note 75 for recommended pad and trace dimensions to avoid solder joint fatigue.
Do not confuse the EPM5064LC (plastic OTP, 55 ns) with the EPM5064LC-1 (faster 30 ns) or EPM5064JC (windowed ceramic). The windowed JC variant allows UV erasure and reprogramming - useful for development but ~10x more expensive and larger. Also note: the EPM5064LC does NOT support in-system programming (ISP) - the older MAX 5000 family requires a separate programmer like the Altera Master Programming Unit or a third-party BP Microsystems / Data I/O programmer.
The EPM5064LC's 24 mA output drive creates fast edge rates (~2 ns) that can cause transmission-line effects on traces longer than 50 mm. Series-damping resistors of 22-33 ohm placed close to the CPLD output may be required for long PCB traces. The 7 dedicated input pins have TTL thresholds with hysteresis and are recommended for asynchronous signals (interrupts, resets) to avoid metastability. Synchronous signals should be routed to macrocell I/O pins with the input flip-flop sampled on the system clock.
Compliance Information
The EPM5064LC is a pre-RoHS legacy part from the MAX 5000 family (originally released ~1990s); the original plastic OTP package is not RoHS compliant. RoHS-compliant variants exist in the MAX 7000AE and later families, but not in MAX 5000. For RoHS-compliant legacy-equivalent designs, migrate to EPM3064ATC44-10 (MAX 3000A family) which is lead-free and RoHS compliant.
