EPM5064LC-2 vs EPM5064JC-1 Comparison
Detailed side-by-side comparison of EPM5064LC-2 by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064LC-2 | EPM5064JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $18.25 |
| Device Family | MAX 5000 | β |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 64 | β |
| Logic Array Blocks (LABs) | 4 | β |
| Logic Elements per LAB | 16 | β |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | β |
| Number of I/O Pins | 28 | β |
| Number of Flip-Flops | 28 | β |
| Propagation Delay (tPD) | 45 ns | β |
| Maximum Internal Frequency | 40 MHz | β |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | 0.8 Β΅m CMOS |
| Programmable Polarity | Yes | β |
| Programmable Output Enable | Yes, per macrocell | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal (4.75 V β 5.25 V) |
| Operating Temperature | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | 0 Β°C to +70 Β°C (commercial, -JC suffix) |
| Package | PLCC-44 (J-Lead, plastic) | 44-pin PLCC (J-lead, windowed ceramic) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket recommended) |
| RoHS Status | [DATA_NEEDED: not specified in source] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Programming Method | Altera byte-wide / JTAG programmer | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| Family | β | MAX 5000 |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | β | 64 |
| Usable Gates | β | 1250 (typical) |
| Logic Elements | β | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | β | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | β | [DATA_NEEDED: tPD typical/max in ns] |
| Programmable Pins | β | 36 (typical I/O, 44-pin PLCC) |
| Dedicated Inputs | β | [DATA_NEEDED: dedicated input count] |
| Erasure Method | β | UV-erasable through quartz window |
| JTAG Boundary Scan | β | Not supported (classic MAX architecture) |
| Military/Avionics SMD | β | 5962-01-417-3750 (QML variant: EPM5064JM/883) |